The AMIC Direct Bus Alternation™ (DBA™) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L83161, A67L83181, A67L73321, A67L73361 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during WriteRead alternation.
■ Fast access time: 10/11/12 ns (100, 90, 83 MHz)
■ Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization
■ Signal +3.3V ± 5% power supply
■ Individual Byte Write control capability
■ Clock enable (CEN) pin to enable clock and suspend operations
■ Clock-controlled and registered address, data and control signals
■ Registered output for pipelined applications
■ Three separate chip enables allow wide range of options for CE control, address pipelining
■ Internally self-timed write cycle
■ Selectable BURST mode (Linear or Interleaved)
■ SLEEP mode (ZZ pin) provided
■ Available in 100 pin LQFP package