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GS881E18BD Datasheet PDF - Giga Semiconductor

Part NameDescriptionManufacturer
GS881E18BD 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs GSI
Giga Semiconductor GSI
Other PDF  2002  
GS881E18BD Datasheet PDF : PDF DOWNLOAD   
GS881E18BD image

Functional Description
Applications
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D) is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA packages
• Pb-Free 100-lead TQFP and 165-bump BGA packages available

 

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