[Freescale]

Overview
The MPC7410 is the second implementation of the fourth generation (G4) microprocessors from Freescale. The MPC7410 implements the full PowerPC 32-bit architecture and is targeted at both computing and embedded systems applications.

Some comments on the MPC7410 with respect to the MPC750:
• The MPC7410 adds an implementation of the new AltiVec™ technology instruction set.
• The MPC7410 includes significant improvements in memory subsystem (MSS) bandwidth and offers an optional, high-bandwidth MPX bus interface.
• The MPC7410 adds full hardware-based multiprocessing capability, including a five-state cache coherency protocol (four MESI states plus a fifth state for shared intervention).
• The MPC7410 is implemented in a next generation process technology for core frequency improvement.
• The MPC7410 floating-point unit has been improved to make latency equal for double- and single-precision operations involving multiplication.
• The completion queue has been extended to eight slots.
• There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms, or the branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch, execute, complete/writeback).

Some comments on the MPC7410 with respect to the MPC7400:
• The MPC7410 adds configurable direct-mapped SRAM capability to the L2 cache interface.
• The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements a 19th L2 address pin (L2ASPARE on the MPC7400) in order to support additional address range.
• The MPC7410 removes support for 3.3-V I/O on the L2 cache interface.