General Description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (DM74S175) versions feature comple mentary outputs from each flip-flop.

Features
■DM74S174 contain six flip-flops with single-rail outputs.
■DM74S175 contain four flip-flops with double-rail outputs.
■Buffered clock and direct clear inputs
■Individual data input to each flip-flop
■Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■Typical clock frequency 110 MHz
■Typical power dissipation per flip-flop 75mW