General Description
This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signals to LVDS levels with a typical differential output swing of 350mV and the receiver translates LVDS signals, with a typical differential input threshold of 100mV, into LVTTL levels. LVDS technology provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed clock or data transfer.

Features
■ Greater than 400Mbs data rate
■ 3.3V power supply operation
■ 0.5ns maximum differential pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ 100mV receiver input sensitivity
■ Fail safe protection open-circuit, shorted and terminated conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Flow-through pinout simplifies PCB layout
■ 14-Lead SOIC and TSSOP packages save space