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74F109

  

Datasheet PDF - Fairchild Semiconductor

74F109 image

Part Name
74F109

Other PDF
  no available.

PDF

page
7 Pages

File Size
76.2 kB

MFG CO.
Fairchild
Fairchild Semiconductor 

General Description
The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs.

Asynchronous Inputs:
   LOW input to SD sets Q to HIGH level
   LOW input to CD sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes
      both Q and Q HIGH


Part Name
Description
PDF
MFC CO.
Dual JK Positive Edge−Triggered Flip−Flop
ON Semiconductor
Dual JK Positive Edge-Triggered Flip-Flop
ON Semiconductor
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
Dual JK Positive Edge−Triggered Flip−Flop ( Rev : 2001 )
ON Semiconductor
Dual JK Positive Edge-Triggered Flip-Flop
ON Semiconductor
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
Dual JK positive edge-triggered flip-flop
Motorola => Freescale
Dual JK Positive Edge−Triggered Flip−Flop
ON Semiconductor
Dual JK Positive Edge-Triggered Flip-Flop
AVG Semiconductors=>HITEK
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale

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