Features
• Up to 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates)
• Highly Predictable Performance with 100% Automatic  Placement and Routing
• 7.5 ns Clock-to-Output Times
• Up to 250 MHz On-Chip Performance
• Up to 228 User-Programmable I/O Pins
• Four Fast, Low-Skew Clock Networks
• More than 500 Macro Functions
• Replaces up to twenty 32 macro-cell CPLDs
• Replaces up to one hundred 20-pin PAL® Packages
• Up to 1153 Dedicated Flip-Flops
• VQFP, TQFP, BGA, and PQFP Packages
• Nonvolatile, User Programmable
• Fully Tested Prior to Shipment
• 5.0V and 3.3V Versions
• Optimized for Logic Synthesis Methodologies
• Low-power CMOS Technology