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Part NameJS28F128P30BF65 Numonyx
Numonyx -> Micron Numonyx
DescriptionNumonyxĀ® Axcellā„¢ P30-65nm Flash Memory 128-Mbit, 64-Mbit Single Bit per Cell (SBC)
JS28F128P30BF65 Datasheet PDF : JS28F128P30BF65 pdf   

Image Info : [Numonyx] PC28F128P30BF65A

This document provides information about the NumonyxĀ® AxcellTM P30-65nm Single Bit per Cell (SBC) Flash memory and describes its features, operations, and specifications.
P30-65nm SBC device is offered in 64-Mbit and 128-Mbit. Benefits include high-speed interface NOR device, and support for code and data storage. Features include high performance synchronous-burst read mode, a dramatical improvement in buffer program time through larger buffer size, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices.
P30-65nm SBC device is manufactured using 65nm process technology.

P30-65nm SBC device provides high performance on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power-up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register (RCR) enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates technology that enables fast buffer program and erase operations. The device features a 256-word buffer to enable optimum programming performance, which can improve system programming throughput time significantly to 1.8MByte/s.

Product Features
ā–  High Performance:
   ā€” 65ns initial access time for Easy BGA and QUAD+
   ā€” 75ns initial access time for TSOP
   ā€” 25ns 8-word asynchronous-page read mode
   ā€” 52MHz with zero WAIT states, 17ns clock-to
      data output synchronous-burst read mode
   ā€” 4-, 8-, 16- and continuous-word options for burst mode
   ā€” 1.8V Low Power buffered programming at
      1.8MByte/s (Typ) using 256-word buffer
   ā€” Buffered Enhanced Factory Programming at
      3.2MByte/s (typ) using 256-word buffer
ā–  Architecture:
   ā€” Asymmetrically-blocked architecture
   ā€” Four 32-KByte parameter blocks: top or bottom configuration
   ā€” 128-KByte array blocks
   ā€” Blank Check to verify an erased block
ā–  Voltage and Power:
   ā€” VCC (core) voltage: 1.7V ā€“ 2.0V
   ā€” VCCQ (I/O) voltage: 1.7V ā€“ 3.6V
   ā€” Standby current: 30ĀµA(Typ)/55ĀµA(Max)
   ā€” Continuous synchronous read current: 23mA (Typ)/28mA (Max) at 52MHz
ā–  Enhanced Security:
   ā€” Absolute write protection: VPP = Vss
   ā€” Power-transition erase/program lockout
   ā€” Individual zero-latency block locking
   ā€” Individual block lock-down capability
   ā€” Password Access feature
   ā€” One-Time Programmable Register:
   ā€” 64 OTP bits, programmed with unique information by Numonyx
   ā€” 2112 OTP bits, available for customer programming
ā–  Software:
   ā€” 20Āµs (Typ) program suspend
   ā€” 20Āµs (Typ) erase suspend
   ā€” Basic Command Set and Extended Function
      Interface (EFI) Command Set compatible
   ā€” Common Flash Interface capable
ā–  Density and Packaging:
   ā€” 56-Lead TSOP (128-Mbit, 64-Mbit)
   ā€” 64-Ball Easy BGA (128-Mbit, 64-Mbit)
   ā€” 88-Ball QUAD+ Package (128-Mbit)
   ā€” 16-bit wide data bus
ā–  Quality and Reliability:
   ā€” JESD47E Compliant
   ā€” Operating temperature: ā€“40Ā°C to +85Ā°C
   ā€” Minimum 100,000 erase cycles
   ā€” 65nm process technology

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