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ADI
Analog Devices
Description : 1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

GENERAL DESCRIPTION
The AD9514 features a multi-output Clock Distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.
There are three independent Clock Outputs. Two of the Outputs are LVPECL, and the third output can be set to either LVDS or CMOS levels. The LVPECL Outputs operate to 1.6 GHz, and the third output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.

FEATURES
   1.6 GHz differential Clock input
   3 programmable Dividers
      Divide-by in range from1 to 32
      Phase select for coarse Delay Adjust
   2 independent 1.6 GHz LVPECL Clock Outputs
      Additive broadband output jitter 225 fs rms
   1 independent 800 MHz/250 MHz LVDS/CMOS Clock output
      Additive broadband output jitter 300 fs rms/290 fs rms
      Time Delays up to 10 ns
   Device configured with 4-level logic pins
   Space-saving, 32-lead LFCSP

APPLICATIONS
   Low jitter, low phase noise Clock Distribution
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
   High performance wireless transceivers
   High performance instrumentation
   Broadband infrastructure
   ATE

Description : 1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

GENERAL DESCRIPTION
The AD9511 provides a multi-output Clock Distribution function along with an on-chip PLL Core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
   Low phase noise phase-locked loop Core
      Reference input frequencies to 250 MHz
      Programmable dual-modulus prescaler
      Programmable charge pump (CP) current
      Separate CP supply (VCPS) extends tuning range
   Two 1.6 GHz, differential Clock inputs
   5 programmable Dividers, 1 to 32, all integers
   Phase select for output-to-output coarse Delay Adjust
   3 independent 1.2 GHz LVPECL Outputs
      Additive output jitter 225 fs rms
   2 independent 800 MHz/250 MHz LVDS/CMOS Clock Outputs
      Additive output jitter 275 fs rms
      Fine Delay Adjust on 1 LVDS/CMOS output
   Serial control port
   Space-saving 48-lead LFCSP

APPLICATIONS
   Low jitter, low phase noise Clock Distribution
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
   High performance wireless transceivers
   High performance instrumentation
   Broadband infrastructure

ADI
Analog Devices
Description : 1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

GENERAL DESCRIPTION
The AD9550 is a phase-locked loop (PLL) based Clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended input reference signal at the REF input.

FEATURES
   Converts preset standard input frequencies to standard
      output frequencies
   Input frequencies from 8 kHz to 200 MHz
   Output frequencies up to 810 MHz LVPECL and LVDS
      (200 MHz CMOS)
   Preset pin-programmable frequency translation ratios
   On-chip VCO
   Single-ended CMOS reference input
   Two output Clocks (independently programmable as LVDS,
      LVPECL, or CMOS)
   Single supply (3.3 V)
   Very low power: <450 mW (under most conditions)
   Small package size (5 mm × 5 mm)
   Exceeds Telcordia GR-253-Core jitter generation, transfer
      and tolerance specifications

APPLICATIONS
   Cost effective replacement of high frequency VCXO, OCXO,
      and SAW resonators
   Flexible frequency translation for wireline applications such
      as Ethernet, T1/E1, SONET/SDH, GPON, xDSL
   Wireless infrastructure
   Test and measurement (including handheld devices)

ADI
Analog Devices
Description : 1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

GENERAL DESCRIPTION
The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended and differential operation.

FEATURES
   Translation between any two standard network rates
   Dual reference inputs and dual Clock Outputs
   Pin programmable for standard network rate translation
   SPI programmable for arbitrary rational rate translation
   Output frequencies from 10 MHz to 900 MHz
   Input frequencies from 19.44 MHz to 806 MHz
   On-chip VCO
   Meets OC-192 high band jitter generation requirement
   Supports standard forward error correction (FEC) rates
   Supports holdover operation
   Supports hitless switchover and phase build-out (even with
      unequal reference frequencies)
   SPI-compatible 3-wire programming interface
   Single supply (3.3 V)

APPLICATIONS
   Multiservice switches
   Multiservice routers
   Exact network Clock frequency translation
   General-purpose frequency translation

ADI
Analog Devices
Description : 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION
The AD9510 provides a multi-output Clock Distribution function along with an on-chip phase-locked loop (PLL) Core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device.

FEATURES
   Low phase noise phase-locked loop Core
      Reference input frequencies to 250 MHz
      Programmable dual modulus prescaler
      Programmable charge pump (CP) current
      Separate CP supply (VCPS) extends tuning range
   Two 1.6 GHz, differential Clock inputs
   8 programmable Dividers, 1 to 32, all integers
   Phase select for output-to-output coarse Delay Adjust
   4 independent 1.2 GHz LVPECL Outputs
      Additive output jitter of 225 fs rms
   4 independent 800 MHz low voltage differential signaling
      (LVDS) or 250 MHz complementary metal oxide conductor
      (CMOS) Clock Outputs
      Additive output jitter of 275 fs rms
      Fine Delay Adjust on 2 LVDS/CMOS Outputs
   Serial control port
   Space-saving 64-lead LFCSP
  
APPLICATIONS
   Low jitter, low phase noise Clock Distribution
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and
      mixed-signal front ends (MxFEs)
   High performance wireless transceivers
   High performance instrumentation
   Broadband infrastructure

Description : 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION
The AD9510 provides a multi-output Clock Distribution function along with an on-chip phase-locked loop (PLL) Core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device.

FEATURES
   Low phase noise phase-locked loop Core
      Reference input frequencies to 250 MHz
      Programmable dual modulus prescaler
      Programmable charge pump (CP) current
      Separate CP supply (VCPS) extends tuning range
   Two 1.6 GHz, differential Clock inputs
   8 programmable Dividers, 1 to 32, all integers
   Phase select for output-to-output coarse Delay Adjust
   4 independent 1.2 GHz LVPECL Outputs
      Additive output jitter of 225 fs rms
   4 independent 800 MHz low voltage differential signaling
      (LVDS) or 250 MHz complementary metal oxide conductor
      (CMOS) Clock Outputs
      Additive output jitter of 275 fs rms
      Fine Delay Adjust on 2 LVDS/CMOS Outputs
   Serial control port
   Space-saving 64-lead LFCSP
  
APPLICATIONS
   Low jitter, low phase noise Clock Distribution
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and
      mixed-signal front ends (MxFEs)
   High performance wireless transceivers
   High performance instrumentation
   Broadband infrastructure

Part Name(s) : AD9515/PCB
ADI
Analog Devices
Description : 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION
The AD9515 features a two-output Clock Distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
   1.6 GHz differential Clock input
   2 programmable Dividers
      Divide-by in range from1 to 32
      Phase select for coarse Delay Adjust
   1.6 GHz LVPECL Clock output
      Additive output jitter 225 fs rms
   800 MHz/250 MHz LVDS/CMOS Clock output
      Additive output jitter 300 fs rms/290 fs rms
      Time Delays up to 10 ns
   Device configured with 4-level logic pins
   Space-saving, 32-lead LFCSP
  
APPLICATIONS
   Low jitter, low phase noise Clock Distribution
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
   High performance wireless transceivers
   High performance instrumentation
   Broadband infrastructure
   ATE

Description : 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION
The AD9512 provides a multi-output Clock Distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part.
There are five independent Clock Outputs. Three Outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.

FEATURES
  Two 1.6 GHz, differential Clock inputs
  5 programmable Dividers, 1 to 32, all integers
  Phase select for output-to-output coarse Delay Adjust
  3 independent 1.2 GHz LVPECL Outputs
     Additive output jitter 225 fs rms
  2 independent 800 MHz/250 MHz LVDS/CMOS Clock Outputs
     Additive output jitter 275 fs rms
     Fine Delay Adjust on 1 LVDS/CMOS output
  Serial control port
  Space-saving 48-lead LFCSP

APPLICATIONS
  Low jitter, low phase noise Clock Distribution
  Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  High performance wireless transceivers
  High performance instrumentation
  Broadband infrastructure

Description : 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION
The AD9513 features a three-output Clock Distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
    1.6 GHz differential Clock input
    3 programmable Dividers
        Divide-by in range from1 to 32
        Phase select for coarse Delay Adjust
    Three 800 MHz/250 MHz LVDS/CMOS Clock Outputs
        Additive output jitter 300 fs rms
        Time Delays up to 11.6 ns
    Device configured with 4-level logic pins
    Space-saving, 32-lead LFCSP

APPLICATIONS
    Low jitter, low phase noise Clock Distribution
    Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
    High performance wireless transceivers
    High performance instrumentation
    Broadband infrastructure
    ATE

Description : 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION
The AD9515 features a two-output Clock Distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
   1.6 GHz differential Clock input
   2 programmable Dividers
      Divide-by in range from1 to 32
      Phase select for coarse Delay Adjust
   1.6 GHz LVPECL Clock output
      Additive output jitter 225 fs rms
   800 MHz/250 MHz LVDS/CMOS Clock output
      Additive output jitter 300 fs rms/290 fs rms
      Time Delays up to 10 ns
   Device configured with 4-level logic pins
   Space-saving, 32-lead LFCSP
  
APPLICATIONS
   Low jitter, low phase noise Clock Distribution
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
   High performance wireless transceivers
   High performance instrumentation
   Broadband infrastructure
   ATE

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