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Part Name(s) : CD4051B-Q1 CD4051BQM96Q1 CD4051BQPWRG4Q1 CD4051BQPWRQ1 CD4051Q CD4052B-Q1 CD4052BQM96Q1 CD4052BQPWRQ1 CD4052Q CD4053B-Q1 CD4053BQM96G4Q1 CD4053BQM96Q1 CD4053BQPWRQ1 CD4053Q CM051BQ TI
Texas Instruments
Description : CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION

description/ordering information
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have low ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved by digital signal amplitudes of 4.5 V to 20 V (If VDD − VSS = 3 V, a VDD − VEE of up to 13 V can be controlled; for VDD − VEE level differences above 13 V, a VDD − VSS of at least 4.5 V is required). For example, if VDD = 4.5 V, VSS = 0 V, and VEE = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD − VSS and VDD − VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic high (H) is present at the inhibit (INH) input, all channels are off.

Features
● Qualified for Automotive Applications
● Wide Range of Digital and Analog Signal
   Levels
   − Digital: 3 V to 20 V
   − Analog: ● 20 VP-P
● Low ON Resistance, 125 Ω (Typ) Over
   15 VP-P Signal Input Range
   for VDD − VEE = 18 V
● High OFF Resistance, Channel Leakage of
   100 pA (Typ) at VDD − VEE = 18 V
● Logic-Level Conversion for Digital
   Addressing Signals of 3 V to 20 V
   (VDD − VSS = 3 V to 20 V) to Switch Analog
   Signals to 20 VP-P (VDD − VEE = 20 V)
● Matched Switching Characteristics,
   ron = 5 Ω (Typ) for VDD − VEE = 15 V
● Very Low Quiescent Power Dissipation
   Under All Digital-Control Input and Supply
   Conditions, 0.2 µW (Typ)
   at VDD − VSS = VDD − VEE = 10 V
● Binary Address Decoding on Chip
● 5-V, 10-V, and 15-V Parametric Ratings
● 100% Tested for Quiescent Current at 20 V
● Maximum Input Current of 1µA at 18 V Over
   Full Package Temperature Range, 100 nA at
   18 V and 25°C
● Break-Before-Make Switching Eliminates
   Channel Overlap

Applications
● Analog and Digital Multiplexing and
   Demultiplexing
● Analog-to-Digital (A/D) and
   Digital-to-Analog (D/A) Conversion
● Signal Gating

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Part Name(s) : TW8816 TW8816_13 Renesas
Renesas Electronics
Description : LCD Flat Panel Processor with built-in MCU, NTSC/PAL/SECAM Decoder, T-CON and Analog RGB Support

The TW8816 is a highly integrated multi-purpose LCD display solution for both analog and digital panels. To reduce BOM cost, TW8816 integrates an 8-bit MCU and a CCFL controller.
Through multiple input ports, TW8816 can directly display video and graphic content from a variety of devices including TV Tuners, DVD players, back-up cameras, DTV/DMB receivers and navigation/GPS receivers.

Features
• Supports analog inputs including CVBS, S-Video, YPbPr &
   RGB signals and digital inputs including 24 bit RGB &
   8/16/24 bit YCbCr. Interlaced and progressive ITU 601
   inputs are supported.
• Supports digital panels up to WXGA resolutions
• Integrates cost saving features including a CCFL controller,
   charge pump booster, programmable panel offset control
   and on-chip 8 bit 8051 MCU with SPI interface
• Embedded Image Enhancement
   - Programmable CTI, hue, brightness, saturation, contrast
      & sharpness control
   - Black/White Stretch
   - Programmable favorite color enhancement- up to three colors
   - Programmable Gamma Correction tables
  
Features List
Analog Video Decoder
• NTSC (M, 4.34) and PAL (B, D, G, H, I, M, N, N combination),
   PAL (60), SECAM with automatic format detection
• Advanced synchronization processing for VCR trick play signal
• Three 10-bit ADCs and analog clamping circuit.
• Built-in analog anti-aliasing filter
• Fully programmable static gain or automatic gain control
   for the Y or CVBS channel
• Programmable white peak control for the Y or CVBS channel
• Software selectable analog inputs allows any of the following
   - Up to 4 composite video
   - UP to 3 S-Video
   - Up to 2 analog YPbPr and RGB
• 4-H adaptive comb filter Y/C separation
• PAL delay line for color phase error correction
• Digital PLL for both color and horizontal locking
• Programmable hue, brightness, saturation, contrast,
   sharpness, Gamma control, and noise suppression
• Automatic color control and color killer
• Detection of level of copy protection according to Macrovision standard

Analog RGB / YPbPr input
• Built-in sync processor for SOG support
• Built-in Line-locked PLL
• Built-in input measurement function
• Support directly sampling up to SVGA(50MHz).

Digital interface
• Allows connection to 8/16/24-bit RGB/YCbCr
• Support interlaced
• ITU 656, interlaced and progressive ITU 601.

TFT Panel Support
• Supports a variety of Digital single pixel TFT panels and
   Analog active matrix TFT panels
• Supports digital TTL panel up to WXGA(1280 x 768),
   100MHz and analog panel up to WQVGA (480 x 234), 20 MHz
• Supports 3, 4, 6 or 8 bits per pixel format (Continue ...)

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Part Name(s) : 56F8000 56F8023 56F8033 MC56F8023 MC56F8023VLC MC56F8033 MC56F8033VLC MC56F8033/56F8023 MC56F8033/56F8023E Freescale
Freescale Semiconductor
Description : 16-bit Digital Signal Controllers

56F8033/56F8023 Description
The 56F8033/56F8023 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8033/56F8023 is well-suited for many applications. The 56F8033/56F8023 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general-purpose inverters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications.
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.

56F8033/56F8023 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• 56F8033 offers 64KB (32K x 16) Program Flash
• 56F8023 offers 32KB (16K x 16) Program Flash
• 56F8033 offers 8KB (4K x 16) Unified Data/Program RAM
• 56F8023 offers 4KB (2K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters (ADCs)
• Two Internal 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI) with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package

56F8033/56F8023 Features
Digital Signal Controller Core
• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging

Memory
• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
• On-chip memory— Master and slave modes
— Four-words-deep FIFOs available on both transmitter and receiver
— Programmable Length Transactions (2 to 16 bits)
• One Inter-Integrated Circuit (I2C) port
— Operates up to 400kbps
— Supports both master and slave operation
— Supports both 10-bit address mode and broadcasting mode
• One 16-bit Programmable Interval Timer (PIT)
• Two analog Comparators (CMPs)
— Selectable input source includes external pins, DACs
— Programmable output polarity
— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
• Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance
• Integrated Power-On Reset and Low-Voltage Interrupt Module
• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
• Clock sources:
— On-chip relaxation oscillator
— External clock: Crystal oscillator, ceramic resonator, and external clock source
• JTAG/EOnCE debug programming interface for real-time debugging
1.1.5 Energy Information
• Fabricated in high-density CMOS with 5V tolerance
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power

   — 64KB of Program Flash (56F80233 device)
     32KB of Program Flash (56F8023 device)
   — 8KB of Unified Data/Program RAM (56F8033 device)
     4KB of Unified Data/Program RAM (56F8023 device)
• EEPROM emulation capability using Flash

Peripheral Circuits for 56F8033/56F8023
• One multi-function six-output Pulse Width Modulator (PWM) module
   — Up to 96MHz PWM operating clock
   — 15 bits of resolution
   — Center-aligned and edge-aligned PWM signal mode
   — Four programmable fault inputs with programmable digital filter
   — Double-buffered PWM registers
   — Each complementary PWM signal pair allows selection of a PWM supply source from:
   – PWM generator
   – External GPIO
   – Internal timers
   – Analog comparator outputs
   – ADC conversion result which compares with values of ADC high- and low-limit registers to set PWM output
• Two independent 12-bit Analog-to-Digital Converters (ADCs)
   — 2 x 3 channel inputs
   — Supports both simultaneous and sequential conversions
   — ADC conversions can be synchronized by both PWM and timer modules
   — Sampling rate up to 2.67MSPS
   — 16-word result buffer registers
• Two internal 12-bit Digital-to-Analog Converters (DACs)
   — 2 μs settling time when output swing from rail to rail
   — Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and range
• One 16-bit multi-purpose Quad Timer module (TMR)
   — Up to 96MHz operating clock
   — Eight independent 16-bit counter/timers with cascading capability
   — Each timer has capture and compare capability
   — Up to 12 operating modes
• One Queued Serial Communication Interface (QSCI) with LIN Slave functionality
   — Full-duplex or single-wire operation
   — Two receiver wake-up methods:
   – Idle line
   – Address mark
   — Four-bytes-deep FIFOs are available on both transmitter and receiver
• One Queued Serial Peripheral Interfaces (QSPI)
   — Full-duplex operation
   — Master and slave modes
   — Four-words-deep FIFOs available on both transmitter and receiver
   — Programmable Length Transactions (2 to 16 bits)
• One Inter-Integrated Circuit (I2C) port
   — Operates up to 400kbps
   — Supports both master and slave operation
   — Supports both 10-bit address mode and broadcasting mode
• One 16-bit Programmable Interval Timer (PIT)
• Two analog Comparators (CMPs)
   — Selectable input source includes external pins, DACs
   — Programmable output polarity
   — Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
   — Output falling and rising edge detection able to generate interrupts
• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
• Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance
• Integrated Power-On Reset and Low-Voltage Interrupt Module
• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
• Clock sources:
   — On-chip relaxation oscillator
   — External clock: Crystal oscillator, ceramic resonator, and external clock source
• JTAG/EOnCE debug programming interface for real-time debugging

Energy Information
• Fabricated in high-density CMOS with 5V tolerance
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power

 

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Part Name(s) : CD4051BC CD4051BCM CD4053 CD4051BCMTC CD4051BCMTCX CD4051BCMX CD4051BCN CD4051BCNX CD4051BCSJ CD4051BCSJX CD4052BC CD4052BCM CD4052BCMX CD4052BCN CD4052BCNX CD4052BCSJ CD4052BCSJX CD4053BC CD4053BCM CD4053BCMX CD4053BCN CD4053BCNX CD4053BCSJ CD4053BCSJX Fairchild
Fairchild Semiconductor
Description : Single 8-Channel Analog Multiplexer/Demultiplexer,Dual 4-Channel Analog Multiplexer/Demultiplexer,Triple 2-Channel Analog Multiplexer/Demultiplexer

General Description
The CD4051BC, CD4052BC, and CD4053BC analog multiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15V p-p can be achieved by digital signal amplitudes of 3−15V. For example, if VDD =5V, VSS =0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0−5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD−VSS and VDD−VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”.

Features
■ Wide range of digital and analog signal levels:
   digital 3 – 15V, analog to 15Vp-p
■ Low “ON” resistance: 80Ω(typ.) over entire 15Vp-p
   signal-input range for VDD −VEE =15V
■ High “OFF” resistance:
   channel leakage of ±10 pA (typ.) at VDD −VEE =10V
■ Logic level conversion for digital addressing signals of
   3 – 15V (VDD −VSS =3 – 15V) to switch analog signa
   to 15 Vp-p(VDD −VEE =15V)
■ Matched switch characteristics:
   ∆RON =5Ω(typ.) for VDD −VEE =15V
■ Very low quiescent power dissipation under all
   digital-control input and supply conditions:
   1 µW (typ.) at VDD −VSS =VDD −VEE =10V
■ Binary address decoding on chip

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Part Name(s) : AD7607 AD7607BSTZ AD7607BSTZ-RL EVAL-AD7607SDZ EVAL-SDP-CB1Z AD7607 AD7607BSTZ AD7607BSTZ-RL EVAL-AD7607EDZ CED1Z ADI
Analog Devices
Description : 8-Channel DAS with 14-Bit, Bipolar Input, Simultaneous Sampling ADC

GENERAL DESCRIPTION
The AD76071 is a 14-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection; a second-order antialiasing filter; a track and-hold amplifier; a 14-bit charge redistribution, successive approximation analog-to-digital converter (ADC); a flexible digital filter; a 2.5 V reference and reference buffer; and high speed serial and parallel interfaces.

FEATURES
   8 simultaneously sampled inputs
   True bipolar analog input ranges: ±10 V, ±5 V
   Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE
   Fully integrated data acquisition solution
      Analog input clamp protection
      Input buffer with 1 MΩ analog input impedance
      Second-order antialiasing analog filter
      On-chip accurate reference and reference buffer
      14-bit ADC with 200 kSPS on all channels
   Flexible parallel/serial interface
      SPI/QSPI™/MICROWIRE™/DSP compatible
   Pin-compatible solutions from 14 bits to 18 bits
   Performance
      7 kV ESD rating on analog input channels
      Fast throughput rate: 200 kSPS for all channels
      85.5 dB SNR at 50 kSPS
      INL ±0.25 LSB, DNL ±0.25 LSB
      Low power: 100 mW at 200 kSPS
      Standby mode: 25 mW typical
   64-lead LQFP package

APPLICATIONS
   Power-line monitoring and protection systems
   Multiphase motor control
   Instrumentation and control systems
   Multiaxis positioning systems
   Data acquisition systems (DAS)

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Part Name(s) : AD7608 AD7608BSTZ AD7608BSTZ-RL EVAL-AD7608EDZ ADI
Analog Devices
Description : 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC

GENERAL DESCRIPTION
The AD7608 is an 18-bit, 8-channel simultaneous sampling, analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces.

FEATURES
   8 simultaneously sampled inputs
   True bipolar analog input ranges: ±10 V, ±5 V
   Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE
   Fully integrated data acquisition solution
      Analog input clamp protection
      Input buffer with 1 MΩ analog input impedance
      Second-order antialiasing analog filter
      On-chip accurate reference and reference buffer
      18-bit ADC with 200 kSPS on all channels
      Oversampling capability with digital filter
   Flexible parallel/serial interface
   SPI/QSPI™/MICROWIRE™/DSP compatible
   Pin compatible solutions from 14-bits to 18-bits
   Performance
      7 kV ESD rating on analog input channels
      98 dB SNR, −107 dB THD
      Low power: 100 mW
      Standby mode: 25 mW
   64-lead LQFP package

APPLICATIONS
   Power line monitoring and protection systems
   Multiphase motor controls
   Instrumentation and control systems
   Multiaxis positioning systems
   Data acquisition systems (DAS)

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Part Name(s) : AD7609 AD7609BSTZ AD7609BSTZ-RL EVAL-AD7609EDZ ADI
Analog Devices
Description : 8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC

GENERAL DESCRIPTION
The AD7609 is an 18-bit, 8-channel, true differential, simultaneous sampling analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces.

FEATURES
   8 simultaneously sampled inputs
   True differential inputs
   True bipolar analog input ranges: ±10 V, ±5 V
   Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE
   Fully integrated data acquisition solution
      Analog input clamp protection
      Input buffer with 1 MΩ analog input impedance
      Second-order antialiasing analog filter
      On-chip accurate reference and reference buffer
      18-bit ADC with 200 kSPS on all channels
      Oversampling capability with digital filter
   Flexible parallel/serial interface
   SPI/QSPI™/MICROWIRE™/DSP compatible
   Performance
      7 kV ESD rating on analog input channels
      98 dB SNR, −107 dB THD
      Dynamic range: up to 105 dB typical
      Low power: 100 mW
      Standby mode: 25 mW
   64-lead LQFP package

APPLICATIONS
   Power line monitoring and protection systems
   Multiphase motor control
   Instrumentation and control systems
   Multiaxis positioning systems
   Data acquisition systems (DAS)

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Part Name(s) : AD1881A AD1881AJST ADI
Analog Devices
Description : AC’97 SoundMAX® Codec

PRODUCT OVERVIEW
The AD1881A meets the Audio Codec ’97 2.0 and 2.1 Extensions. In addition, the AD1881A SoundMAX Codec is designed to meet all requirements of the Audio Codec ’97, Component Specification, Revision 1.03, © 1996, Intel Corporation, found at www.Intel.com. The AD1881A also includes some other Codec enhanced features such as the built-in PHAT Stereo 3D enhancement.
The AD1881A is an analog front end for high performance PC audio applications. The AC’97 architecture defines a 2-chip audio solution comprising a digital audio controller, plus a high quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs), mixer and I/O.
The main architectural features of the AD1881A are the high quality analog mixer section, two channels of Σ∆ ADC conversion, two channels of Σ∆ DAC conversion with Data Direct Scram bling (D2S) rate generators. The AD1881A’s left channel ADC and DAC are compatible for modem applications supporting irrational sample rates and modem filtering requirements.

AC’97 2.1 FEATURES
   Variable Sample Rate
   True Line-Level Output
   Supports Secondary Codec Modes
  
AC’97 FEATURES
   Designed for AC’97 Analog I/O Component
   48-Lead LQFP Package
   Multibit ΣΔ Converter Architecture for Improved
      S/N Ratio Greater than 90 dB
   16-Bit Stereo Full-Duplex Codec
      Four Analog Line-Level Stereo Inputs for Connection
      from LINE, CD, VIDEO, and AUX
   Two Analog Line-Level Mono Inputs for Speakerphone
      and PC BEEP
   Mono MIC Input Switchable from Two External
      Sources
   High Quality CD Input with Ground Sense
   Stereo Line-Level Output
   Mono Output for Speakerphone or Internal Speaker
   Power Management Support

ENHANCED FEATURES
   Mobile Low Power Mixer Mode
   Digital Audio Mixer Mode
   Full Duplex Variable 8 kHz to 48 kHz Sampling Rate
      with 1 Hz Resolution
   PHAT™ Stereo 3D Stereo Enhancement
   Split Power Supplies (3.3 V Digital/5 V Analog)
   Extended 6-Bit Master Volume Control
   Audio Amp Power-Down Signal

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Part Name(s) : 74VHC4051 74VHC4051M 74VHC4051MTC 74VHC4051MTCX 74VHC4051MX 74VHC4051N 74VHC4051NX 74VHC4051WM 74VHC4051WMX 74VHC4052 74VHC4052M 74VHC4052MTC 74VHC4052MTCX 74VHC4052MX 74VHC4052N 74VHC4052NX 74VHC4052WM 74VHC4052WMX 74VHC4053 74VHC4053M 74VHC4053MTC 74VHC4053MTCX 74VHC4053MX 74VHC4053N 74VHC4053NX Fairchild
Fairchild Semiconductor
Description : 8-Channel Analog Multiplexer • Dual 4-Channel Analog Multiplexer • Triple 2-Channel Analog Multiplexer

General Description
These multiplexers are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology. These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog input may be used as an output and vice-versa. Also these
switches contain linearization circuitry which lowers the “on” resistance and increases switch linearity. These devices allow control of up to ±6V (peak) analog signals with digital control signals of 0 to 6V. Three supply pins are provided for VCC, ground, and VEE. This enables the con
nection of 0–5V logic signals when VCC =5V and an analog input range of ±5V when VEE =5V. All three devices also have an inhibit control which when high will disable all switches to their off state. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to VCC and ground.

Features
■Wide analog input voltage range: ±6V
■Low “on” resistance: 50 typ. (VCC–VEE =4.5V)
                              30 typ. (VCC–VEE =9V)
■Logic level translation to enable 5V logic with ±5V analog signals
■Low quiescent current: 80 µA maximum
■Matched switch characteristic
■Pin and function compatible with the 74HC4051/ 4052/4053

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