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Part Name(s) : SAF-XE167FM SAF-XE167GM SAF-XE167HM SAF-XE167KM SAK-XE167FM SAK-XE167FM-48F80L SAK-XE167FM-72F80LAA SAK-XE167GM SAK-XE167HM SAK-XE167HM-72F80L SAK-XE167KM XE167FM XE167GM XE167HM XE167KM Infineon
Infineon Technologies
Description : 16-Bit Single-Chip Real Time Signal Controller

Summary of Features
For a quick overview and easy reference, the features of the XE167xM are summarized here.
• High-performance CPU with five-stage pipeline and MPU
   – 12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution)
   – One-cycle 32-bit addition and subtraction with 40-bit result
   – One-cycle multiplication (16 × 16 bit)
   – Background division (32 / 16 bit) in 21 cycles
   – One-cycle multiply-and-accumulate (MAC) instructions
   – Enhanced Boolean bit manipulation facilities
   – Zero-cycle jump execution
   – Additional instructions to support HLL and operating systems
   – Register-based design with multiple variable register banks
   – Fast context switching support with two additional local register banks
   – 16 Mbytes total linear address space for code and data
   – 1024 Bytes on-chip special function register area (C166 Family compatible)
   – Integrated Memory Protection Unit (MPU)
• Interrupt system with 16 priority levels for up to 96 sources
   – Selectable external inputs for interrupt generation and wake-up
   – Fastest sample-rate 12.5 ns
• Eight-channel interrupt-driven single-cycle data transfer with Peripheral Event Controller (PEC), 24-bit pointers cover total address space
• Clock generation from internal or external clock sources, using on-chip PLL or prescaler
• Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip Memory Areas
• On-chip memory modules
   – 8 Kbytes on-chip stand-by RAM (SBRAM)
   – 2 Kbytes on-chip dual-port RAM (DPRAM)
   – Up to 16 Kbytes on-chip data SRAM (DSRAM)
   – Up to 32 Kbytes on-chip program/data SRAM (PSRAM)
   – Up to 576 Kbytes on-chip program memory (Flash memory)
   – Memory content protection through Error Correction Code (ECC)
• On-Chip Peripheral Modules
   – Multi-functional general purpose timer unit with 5 timers
   – 16-channel general purpose capture/compare unit (CAPCOM2)
   – Up to 4 capture/compare units for flexible PWM signal generation (CCU6x)
   – Two Synchronizable A/D Converters with a total of up to 24 channels, 10-bit resolution, conversion time below 1 μs, optional data preprocessing (data reduction, range check), broken wire detection
   – Up to 8 serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface
   – On-chip MultiCAN interface (Rev. 2.0B active) with up to 128 message objects (Full CAN/Basic CAN) on up to 6 CAN nodes and gateway functionality
   – On-chip system timer and on-chip real time clock
• Up to 12 Mbytes external address space for code and data
   – Programmable external bus characteristics for different address ranges
   – Multiplexed or demultiplexed external address/data buses
   – Selectable address bus width
   – 16-bit or 8-bit data bus width
   – Five programmable chip-select signals
   – Hold- and hold-acknowledge bus arbitration support
• Single power supply from 3.0 V to 5.5 V
• Programmable watchdog timer and oscillator watchdog
• Up to 119 general purpose I/O lines
• On-chip bootstrap loaders
• Supported by a full range of development tools including C compilers, macro assembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyzer disassemblers, programming boards
• On-chip debug support via Device Access Port (DAP) or JTAG interface
• 144-pin Green LQFP package, 0.5 mm (19.7 mil) pitch

 

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Part Name(s) : XC2000_ XC2285 XC2286 XC2287 XC228X SAK-XC2287-96F66L SAK-XC2287-72F66L SAK-XC2287-56F66L SAK-XC2286-96F66L SAK-XC2286-72F66L SAK-XC2286-56F66L SAK-XC2285-96F66L SAK-XC2285-72F66L SAK-XC2285-56F66L Infineon
Infineon Technologies
Description : 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

General Device Information
The XC228x derivatives are high-performance members of the Infineon XC2000 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 66 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. Optimized peripherals can be adapted to the application’s requirements in a flexible way. These derivatives also provide clock generation via PLL and internal or external clock sources, and various on-chip memory modules such as program Flash, program RAM, and data RAM.

Summary of Features
For a quick overview or reference, the XC228x’s properties are listed here in a condensed way.
• High Performance 16-bit CPU with 5-Stage Pipeline
   – 15 ns Instruction Cycle Time at 66 MHz CPU Clock (Single-Cycle Execution)
   – 1-Cycle 32-bit Addition and Subtraction with 40-bit Result
   – 1-Cycle Multiplication (16 × 16 bit)
   – 1-Cycle Multiply-and-Accumulate (MAC) Instructions
   – Background Division (32 / 16 bit) in 21 Cycles
   – Enhanced Boolean Bit Manipulation Facilities
   – Zero-Cycle Jump Execution
   – Additional Instructions to Support HLL and Operating Systems
   – Register-Based Design with Multiple Variable Register Banks
   – Fast Context Switching Support with Two Additional Local Register Banks
   – 16 Mbytes Total Linear Address Space for Code and Data
   – 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with up to 87 Sources, Selectable External Inputs for Interrupt Generation and Wake-Up, Sample-Rate down to 15 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation from Internal or External Clock Sources, via on-chip PLL or via Prescaler
• On-Chip Memory Modules
   – 1 Kbyte On-Chip Stand-By RAM (SBRAM)
   – 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
   – 16 Kbytes On-Chip Data SRAM (DSRAM)
   – Upt to 64 Kbytes On-Chip Program/Data SRAM (PSRAM)
   – Up to 768 Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
   – Two Synchronizable A/D Converters with a total of 24 Channels, 10-bit Resolution, Conversion Time down to 1.2 µs, Optional Data Preprocessing (Data Reduction, Range Check)
   – 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
   – Up to four Capture/Compare Units for flexible PWM Signal Generation (CCU6x)
   – Multi-Functional General Purpose Timer Unit with 5 Timers
   – Six Serial Interface Channels to be used as UART, LIN, High-Speed Synchronous Channel (SPI/QSPI), IIC Bus Interface (10-bit addressing, 400 kbit/s), IIS Interface
   – On-Chip MultiCAN Interface (Rev. 2.0B active) with 128 Message Objects
      (Full CAN/Basic CAN) on up to 5 CAN Nodes and Gateway Functionality
   – On-Chip Real Time Clock
• Up to 12 Mbytes External Address Space for Code and Data
   – Programmable External Bus Characteristics for Different Address Ranges
   – Multiplexed or Demultiplexed External Address/Data Buses
   – Selectable Address Bus Width
   – 16-Bit or 8-Bit Data Bus Width
   – Five Programmable Chip-Select Signals
   – Hold- and Hold-Acknowledge Bus Arbitration Support
• Single Power Supply from 3.0 V to 5.5 V
• Power Reduction Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 118 General Purpose I/O Lines
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers, Macro Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 144-Pin Green LQFP Package, 0.5 mm (19.7 mil) pitch

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Part Name(s) : SAF-XC161CJ-16F20F_02 SAF-XC161CJ-16F40F_02 SAK-XC161CJ-16F20F_02 SAK-XC161CJ-16F40F_02 XC161CJ XC161CJ SAK-XC161CJ-16F40F_03 SAK-XC161CJ-16F20F_03 SAF-XC161CJ-16F40F_03 SAF-XC161CJ-16F20F_03 Infineon
Infineon Technologies
Description : 16-Bit Single-Chip Microcontroller

General Device Information
Introduction
The XC161 derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 40 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program Flash, program RAM, and data RAM.

Summary of Features
• High Performance 16-bit CPU with 5-Stage Pipeline
   – 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
   – 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
   – 1-Cycle Multiply-and-Accumulate (MAC) Instructions
   – Enhanced Boolean Bit Manipulation Facilities
   – Zero-Cycle Jump Execution
   – Additional Instructions to Support HLL and Operating Systems
   – Register-Based Design with Multiple Variable Register Banks
   – Fast Context Switching Support with Two Additional Local Register Banks
   – 16 Mbytes Total Linear Address Space for Code and Data
   – 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with 74 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 …1:10), or via Prescaler (factors 1:1 …60:1)
• On-Chip Memory Modules
   – 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
   – 4 Kbytes On-Chip Data SRAM (DSRAM)
   – 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
   – 128 Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
   – 12-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.55 µs or 2.15 µs)
   – Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
   – Multi-Functional General Purpose Timer Unit with 5 Timers
   – Two Synchronous/Asynchronous Serial Channels (USARTs)
   – Two High-Speed-Synchronous Serial Channels
   – On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects
      (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
   – Serial Data Link Module (SDLM), compliant with J1850, supporting Class 2
   – IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
   – On-Chip Real Time Clock, Driven by Dedicated Oscillator
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 12 Mbytes External Address Space for Code and Data
   – Programmable External Bus Characteristics for Different Address Ranges
   – Multiplexed or Demultiplexed External Address/Data Buses
   – Selectable Address Bus Width
   – 16-Bit or 8-Bit Data Bus Width
   – Five Programmable Chip-Select Signals
   – Hold- and Hold-Acknowledge Bus Arbitration Support
• Up to 99 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

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Part Name(s) : XC161CJ-16F SAK-XC161CJ-16F40F SAK-XC161CJ-16F20F SAF-XC161CJ-16F40F SAF-XC161CJ-16F20F Infineon
Infineon Technologies
Description : 16-Bit Single-Chip Microcontroller with C166SV2 Core

General Device Information
Introduction
The XC161 derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 40 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program Flash, program RAM, and data RAM.

Summary of Features
• High Performance 16-bit CPU with 5-Stage Pipeline
   – 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
   – 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
   – 1-Cycle Multiply-and-Accumulate (MAC) Instructions
   – Enhanced Boolean Bit Manipulation Facilities
   – Zero-Cycle Jump Execution
   – Additional Instructions to Support HLL and Operating Systems
   – Register-Based Design with Multiple Variable Register Banks
   – Fast Context Switching Support with Two Additional Local Register Banks
   – 16 Mbytes Total Linear Address Space for Code and Data
   – 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with 73 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
   – 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
   – 4 Kbytes On-Chip Data SRAM (DSRAM)
   – 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
   – 128 Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
   – 12-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.55 µs or 2.15 µs)
   – Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
   – Multi-Functional General Purpose Timer Unit with 5 Timers
   – Two Synchronous/Asynchronous Serial Channels (USARTs)
   – Two High-Speed-Synchronous Serial Channels
   – On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality)
   – Serial Data Link Module (SDLM), compliant with J1850, supporting Class 2
   – IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
   – On-Chip Real Time Clock, Driven by Dedicated Oscillator
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 12 Mbytes External Address Space for Code and Data
   – Programmable External Bus Characteristics for Different Address Ranges
   – Multiplexed or Demultiplexed External Address/Data Buses
   – Selectable Address Bus Width
   – 16-Bit or 8-Bit Data Bus Width
   – Five Programmable Chip-Select Signals
   – Hold- and Hold-Acknowledge Bus Arbitration Support
• Up to 99 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers, Macro Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

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Part Name(s) : SAF-XC164CS-32F20F SAF-XC164CS-32F40F SAF-XC164CS-32R20F SAF-XC164CS-32R40F SAK-XC164CS-32F20F SAK-XC164CS-32F40F SAK-XC164CS-32R20F SAK-XC164CS-32R40F XC164CS-32F XC164CS-32R Infineon
Infineon Technologies
Description : 16-Bit Single-Chip Microcontroller with C166SV2 Core

General Device Information
Introduction
The XC164CS derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to40 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program Flash, program RAM, and data RAM.

Summary of Features
• High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 ×16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with 75 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 4 Kbytes On-Chip Data SRAM (DSRAM)
– 6 Kbytes On-Chip Program/Data SRAM (PSRAM)
– 256 Kbytes On-Chip Program Memory (Flash Memory or Mask ROM)
• On-Chip Peripheral Modules
– 14-Channel A/D Converter with Programmable Resolution(10-bit or 8-bit) and Conversion Time (down to 2.55 µs or 2.15 µs)
– Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins)
– Capture/Compare Unit for flexible PWM SignalGeneration (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/AsynchronousSerial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
– On-Chip Real Time Clock
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Four Programmable Chip-Select Signals
• Up to 79 General Purpose I/O Lines, partly with Selectable InputThresholds and Hysteresis
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers, Macro Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Supportvia JTAG Interface
• 100-Pin Green TQFP Package, 0.5 mm (19.7 mil) pitch (RoHS compliant)

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Part Name(s) : C164CI C164CI/SI C164CL C164CL/SL C164SI C164SL SAF-C164CI SAF-C164CI-8EM SAF-C164CI-8R25M SAF-C164CI-8RM SAF-C164CI-L25M SAF-C164CI-LM SAF-C164CL SAF-C164CL-6R25M SAF-C164CL-6RM SAF-C164CL-8R25M SAF-C164CL-8RM SAF-C164SI-8R25M SAF-C164SI-8RM SAF-C164SL-6R25M SAF-C164SL-6RM SAF-C164SL-8R25M SAF-C164SL-8RM SAK-C164CI-8EM SAK-C164CI-8R25M Infineon
Infineon Technologies
Description : 16-Bit Single-Chip Microcontroller

Introduction
The C164CI derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers are especially suited for cost sensitive applications. They combine high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM or OTP, internal RAM, and extension RAM.

16-Bit Single-Chip Microcontroller C164CI C166 Family
C164CI/SI, C164CL/SL
• High Performance 16-bit CPU with 4-Stage Pipeline
   – 80 ns Instruction Cycle Time at 25 MHz CPU Clock
   – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
   – Enhanced Boolean Bit Manipulation Facilities
   – Additional Instructions to Support HLL and Operating Systems
   – Register-Based Design with Multiple Variable Register Banks
   – Single-Cycle Context Switching Support
   – 16 MBytes Total Linear Address Space for Code and Data
   – 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
• On-Chip Memory Modules
   – 2 KBytes On-Chip Internal RAM (IRAM)
   – 2 KBytes On-Chip Extension RAM (XRAM)
   – up to 64 KBytes On-Chip Program Mask ROM or OTP Memory
• On-Chip Peripheral Modules
   – 8-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs
   – 8-Channel General Purpose Capture/Compare Unit (CAPCOM2)
   – Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel)
   – Multi-Functional General Purpose Timer Unit with 3 Timers
   – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
   – On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects (Full CAN/Basic CAN)
– On-Chip Real Time Clock
• Up to 4 MBytes External Address Space for Code and Data
   – Programmable External Bus Characteristics for Different Address Ranges
   – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
   – Four Optional Programmable Chip-Select Signals
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 59 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 80-Pin MQFP Package, 0.65 mm pitch

 

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Part Name(s) : EPF011A EPF011C EPF011D ETC
Unspecified
Description : Generic MCU with 64K Embedded Flash

[NON-DISCLOSURE AGREEMENT REQUIRED]

Overview
EPF011A/EPF011C/EPF011D is a low cost high performance Micro Controller. The chip integrates 80515 core, 64KB embedded Flash, 256 + 2KB RAM, Timer, Watchdog Timer, Serial Port, 8-bit PWM, SPI, IIC Slave, IIC Master, 10-bit ADC, USB 1.1, Remote Decoder, Keyboard Interrupt and GPIO in a single chip.

Features
• On-chip 80515 core with 64K bytes Flash, 256 bytes Direct RAM
   and 2K bytes on-chip auxiliary RAM
• Fast CPU rate (24Mhz). 41.6 ns for shortest instruction
• Programmable CPU clocks from 24 Mhz to 500 Khz
• Programmable crystal start-up cycles from 0 to 4096 cycles
• Supports Idle mode and Stop mode for power saving.
• Supports crystal/CPU wake-up from Stop mode
• Supports In Circuit Flash programming (ICP)
• Supports 2 external interrupts
• Supports keyboard interrupt on 4 GPIO pins.
• On-chip 4 Timers supporting Timer, Pulse Output,
   Event Counter and Pulse Width Measurement modes
• On-chip 15-bit programmable Watchdog Timer
• On-chip Serial Port which supports Synchronous mode
   and 8/9-bit UART modes
• On-chip Serial Peripheral Interface (SPI)
• On-chip 4 channels of 8-bit PWM with programmable repetition rate
• On-chip 4 channels of 10-bit ADC
• On-chip IIC Master and Slave ports with configurable pin outs
• On-chip USB 1.1 which supports end-pint 0, 1 and 2
• On-chip Consumer Infra-Red Remote Receiver (CIR)
   which supports NEC and Phillips RC-5 protocols
• EPF011A supports 9 General Purpose I/O Ports (total 44 I/O pins).
   Among them, 6 ports are open-drain programmable and
   2 ports has 20 mA sink capability. All I/O ports are 5V tolerant.
• EPF011D supports 9 General Purpose I/O Ports (total 31 I/O pins).
   Among them, 6 ports are open-drain programmable
   and 2 ports has 20 mA sink capability. All I/O ports are 5V tolerant.
• EPF011C supports 7 General Purpose I/O Ports (total 14 I/O pins).
   Among them, 4 ports are open-drain programmable and 1 ports has 20 mA
   sink capability. All I/O ports are 5V tolerant.
• Timer, SPI and ADC pins can be additional GPIO
   if the associated function is not enabled
• On-chip Low Voltage Inhibit (LVI) circuit which provides
   reliable power up reset and prevent accidental data loss in Flash
• Single 24 MHz crystal required
• Single 3.3V CMOS design
• 64-pin LQFP package (Pb-Free) for EPF011A,
   48-pin LQFP package (Pb-Free) for EPF011D,
   24-Pin SSOP (Pb-Free) for EPF011C

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Part Name(s) : XC164TM SAF-XC164TM-8F40F SAF-XC164TM-8F20F SAF-XC164TM-4F40F SAF-XC164TM-4F20F XC164TM SAF-XC164TM-16F40F SAF-XC164TM-16F20F SAF-XC164TM-8F40F SAF-XC164TM-8F20F SAF-XC164TM-4F40F SAF-XC164TM-4F20F Infineon
Infineon Technologies
Description : 16-Bit Single-Chip Microcontroller with C166SV2 Core

General Device Information
The XC164TM derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 40 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program Flash, program RAM, and data RAM.

Summary of Features
• High Performance 16-bit CPU with 5-Stage Pipeline
   – 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
   – 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
   – 1-Cycle Multiply-and-Accumulate (MAC) Instructions
   – Enhanced Boolean Bit Manipulation Facilities
   – Zero-Cycle Jump Execution
   – Additional Instructions to Support HLL and Operating Systems
   – Register-Based Design with Multiple Variable Register Banks
   – Fast Context Switching Support with Two Additional Local Register Banks
   – 16 Mbytes Total Linear Address Space for Code and Data
   – 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with up to 63 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 2 Kbytes On-Chip Data SRAM (DSRAM, XC164TM-8F only)
– 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
– 64 Kbytes (XC164TM-8F) or 32 Kbytes (XC164TM-4F) On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
   – 14-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.55 µs or 2.15 µs)
   – 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
   – Multi-Functional General Purpose Timer Unit with 5 Timers
   – Two Synchronous/Asynchronous Serial Channels (USARTs)
   – Two High-Speed-Synchronous Serial Channels
   – On-Chip Real Time Clock, Driven by the Main Oscillator
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 47 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• On-Chip Debug Support via JTAG Interface

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Part Name(s) : C167CS-XC Q67120-C2200 Q67120-C2274 Q67120-C2275 SAK-C167CS-4RC SAK-C167CS-LC SAL-C167CS-L33C SAL-C167CS-LC Infineon
Infineon Technologies
Description : 16-Bit Single-Chip Microcontroller Bare Die Delivery

Introduction
The C167CS-xC derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 16.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM.

C167CS-xC
• High Performance 16-bit CPU with 4-Stage Pipeline
   – 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
   – 400/303 ns Multiplication (16 × 16 bit), 800/606 ns Division (32/16 bit)
   – Enhanced Boolean Bit Manipulation Facilities
   – Additional Instructions to Support HLL and Operating Systems
   – Register-Based Design with Multiple Variable Register Banks
   – Single-Cycle Context Switching Support
   – 16 MBytes Total Linear Address Space for Code and Data
   – 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
• On-Chip Memory Modules
   – 3 KBytes On-Chip Internal RAM (IRAM)
   – 8 KBytes On-Chip Extension RAM (XRAM)
   – 32 KBytes On-Chip Program Mask ROM
• On-Chip Peripheral Modules
   – 24-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs
   – Two 16-Channel Capture/Compare Units
   – 4-Channel PWM Unit
   – Two Multi-Functional General Purpose Timer Units with 5 Timers
   – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
   – Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 × 15 Message Objects (Full CAN/Basic CAN), can work on one bus with 30 objects
   – On-Chip Real Time Clock
• Up to 16 MBytes External Address Space for Code and Data
   – Programmable External Bus Characteristics for Different Address Ranges
   – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
   – Five Programmable Chip-Select Signals
   – Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader

 

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