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Part Name(s) : TC4017 TC4017BF TC4017BP Toshiba
ToshibaToshiba
Description : TC4017BP/TC4017BF Decade Counter/Divider

TC4017BP/BF is decimal Johnson counter consisting of 5 stage D-type flip-flop equipped with the decoder to convert the output to decimal. Depending on the number of count pulses fed to CLOCK or CLOCK INHIBIT one output among 10 output lines “Q0” through “Q9” becomes “H” level. The counter advances its state at rising edge of CLOCK (CLOCK INHIBIT = “L”) or falling edge of CLOCK INHIBIT (CLOCK = “H”). RESET input to “H” level resets the counter to Q0 = “H” and Q1 through Q9 = “L” regardless of CLOCK and CLOCK INHIBIT

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Part Name(s) : XRK79892 XRK79892IQ Exar
ExarExar
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

GENERAL DESCRIPTION
The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other
three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packagin
• Pin compatible with MPC9892i

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Part Name(s) : XRK7988 Exar
ExarExar
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

GENERAL DESCRIPTION
The XRK7988 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 8x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packaging
• 19.44 to 155.52 MHz

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Part Name(s) : DM7473 DM7473CW DM7473N Fairchild
FairchildFairchild
Description : Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is HIGH. Data transfers to the outputs on the falling edge of the clock pulse. A LOW logic level on the clear input will reset the outputs regardless of the logic states of the other inputs.

 

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Part Name(s) : SN54LS113A SN54LS113AJ SN54LS113J SN74LS113AD SN74LS113AN SN74LS113D SN74LS113N Motorola
MotorolaMotorola
Description : Dual JK negative edge-triggered flip-flop

The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithicdual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputsmay be allowed to change when the clock pulse is HIGH and the bistablewill perform according to the truth table as longas minimum setup timesare observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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Part Name(s) : MC10131 MC10131FN MC10131L MC10131P Motorola
MotorolaMotorola
Description : Dual Type D Master-Slave Flip-Flop

The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop may be clocked separately by holding the common clock in the low state nd using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock.

PD = 235 mW typ/pkg (No Load)
FTog = 160 MHz typ
tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%–80%)

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Part Name(s) : SN54LS73 SN54LS73AJ SN54LS73J SN74LS73 SN74LS73A SN74LS73AD SN74LS73AN SN74LS73D SN74LS73N Motorola
MotorolaMotorola
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

  TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per formaccording to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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Part Name(s) : HD74LS165A HD74LS165AFP HD74LS165AFPEL HD74LS165AP Renesas
RenesasRenesas
Description : Parallel-Load 8-bit Shift Register

The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift / load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.

Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift / load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the clock, clock inhibit, or serial inputs

 

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Part Name(s) : MC10131 MC10131FN MC10131FNR2 MC10131L MC10131P ON-Semiconductor
ON-SemiconductorON-Semiconductor
Description : Dual Type D Master-Slave Flip-Flop

The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock.

• PD = 235 mW typ/pkg (No Load)
• FTog = 160 MHz typ
• tpd = 3.0 ns typ
• tr, tf = 2.5 ns typ (20%–80%)

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Part Name(s) : 7476 DM7476 DM7476N Fairchild
FairchildFairchild
Description : Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs must not be allowed to change while the clock is HIGH. The data is transferred to the outputs on the falling edge of the clock pulse. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic
levels of the other inputs.

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