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Part Name(s) : HD74LS293 HD74LS293P Renesas
Renesas Electronics
Description : 4-bit Binary Counter

4-bit Binary Counter

This Counter contains four master-slave flip-flops and additional gating to provide a divide-by-two Counter and divide by-eight Counter. This Counter has a gated zero reset. To use the maximum count length of this Counter, the B input is connected to the QAoutput. The input count pulses are applied to input A and the outputs are as described in the appropriate function table.

 

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Part Name(s) : HEF4029B HEF4029BD HEF4029BDB HEF4029BDF HEF4029BF HEF4029BN HEF4029BP HEF4029BPN HEF4029BT HEF4029BTD HEF4029BU Philips
Philips Electronics
Description : Synchronous up/down Counter, binary/decade Counter

DESCRIPTION
The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade Counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3), four parallel buffered outputs (O0 to O3) and an active LOW terminal count output (TC).
Information on P0 to P3 is asynchronously loaded into the Counter while PL is HIGH, independent of CP.
The Counter is advanced one count on the LOW to HIGH transition of CP when CE and PL are LOW. The TC signal is normally HIGH and goes LOW when the Counter reaches its maximum count in the UP mode, or the minimum count in the DOWN mode provided CE is LOW.

 

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Part Name(s) : SN54LS192 SN54LS193 SN54LS193J SN74LS193DR2 ON-Semiconductor
ON Semiconductor
Description : PRESETTABLE BCD/DECADE UP/DOWN Counter PRESETTABLE 4-BIT BINARY UP/DOWN Counter

PRESETTABLE BCD/DECADE UP/DOWN Counter
PRESETTABLE 4-BIT BINARY UP/DOWN Counter

The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage Counter designs. Individual preset inputs allow the circuits to be used as programmable Counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.

• Low Power . . . 95 mW Typical Dissipation
• High Speed . . . 40 MHz Typical Count Frequency
• Synchronous Counting
• Asynchronous Master Reset and Parallel Load
• Individual Preset Inputs
• Cascading Circuitry Internally Provided
• Input Clamp Diodes Limit High Speed Termination Effects

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Part Name(s) : 54HC696 54HC697 54HC698 54HC699 74HC696 74HC697 74HC698 74HC699 M54HC696 M54HC696B1R M54HC696C1R M54HC696F1R M54HC696M1R M54HC697 M54HC697B1R M54HC697C1R M54HC697F1R M54HC697M1R M54HC698 M54HC698B1R M54HC698C1R M54HC698F1R M54HC698M1R M54HC699 M54HC699B1R ST-Microelectronics
STMicroelectronics
Description : HC697/699 U/D 4 BIT BINARY Counter/REGISTER (3-STATE) , HC696/698 U/D DECADE Counter/REGISTER (3-STA

The HC696/697 are high speed CMOS up/down Counters fabricated with silicon gate C2MOS technology.

They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The HC696/698 are BCD DECADE Counter, and the HC697/699 are 4-BIT BINARY Counter. Both devices have register.

They count on the positive edge of the Counter clock input (CCK) when selected by the ”Counter Mode”. If the input U/D is held ”H”, the internal Counter counts up, and held ”L”, counts down.

The internal Counter’s outputs are stored in the output register at the positive edge of register clock (RCK). The Counter features enable P and enable T and a ripple-carry output for easy expansion. the register/Counter select input, R/C, selects the Counter when low or the register when high for the three state outputs, QA, QB, Qc and QD.

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Part Name(s) : 7490 74LS90 74LS90D SN74LS90 SN74LS90DR2 SN74LS90N SN74LS90D SN54LS90J ON-Semiconductor
ON Semiconductor
Description : DECADE Counter; DIVIDE-BY-TWELVE Counter; 4-BIT BINARY Counter

The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type Counters partitioned into two sections. Each Counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 Counters. All of the Counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, Binary
• Input Clamp Diodes Limit High Speed Termination Effects

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Part Name(s) : 74LS90 74LS92 74LS93 SN54LS90J SN54LS92J SN54LS93J SN74LS90N SN74LS92D SN74LS92N SN74LS93D Motorola
Motorola => Freescale
Description : DECADE Counter / DIVIDE-BY-TWELVE Counter / 4-BIT BINARY Counter

The SN54/74LS90, SN54/74LS92 andSN54/74LS93 are high-speed 4-bitripple type Counters partitioned intotwo sections. Each Counter has a divide-by-twosection andeither a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight(LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs.

1. Low Power Consumption . . . Typically 45 mW
2. High Count Rates . . . Typically 42 MHz
3. Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, Binary
4. Input Clamp Diodes Limit High Speed Termination Effects

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Part Name(s) : HD74LS93 HD74LS93FPEL HD74LS93P Renesas
Renesas Electronics
Description : 4-bit Binary Counter

The HD74LS93 contains four master-slave flip-flops and additional gating to provide a divide-by-two Counter and three-state binary Counter for divide-by-eight. To use this maximum count length of this Counter, the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are described in the appropriate function table.

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Part Name(s) : SN54-74LS90 SN54LS90 SN54LS92 SN54LS92J SN54LS93 SN54LS93J SN74LS92 SN74LS92D SN74LS92N SN74LS93 SN74LS93D SN74LS93N ON-Semiconductor
ON Semiconductor
Description : DECADE Counter; DIVIDE-BY-TWELVE Counter; 4-BIT BINARY Counter

The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed 4-bit ripple type Counters partitioned into two sections. Each Counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 Counters. All of the Counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, Binary
• Input Clamp Diodes Limit High Speed Termination Effects

 

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Part Name(s) : SN54-74LS192 SN54-74LS193 SN54/74LS192 SN54/74LS193 SN54LS192J SN54LS193J SN74LS192D SN74LS192N SN74LS193D SN74LS193N Motorola
Motorola => Freescale
Description : PRESETTABLE BCD/DECADE UP/DOWN Counter PRESETTABLE 4-BIT BINARY UP/DOWN Counter

PRESETTABLE BCD/DECADE UP/DOWN Counter PRESETTABLE 4-BIT BINARY UP/DOWN Counter

The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage Counter designs. Individual preset inputs allow the circuits to be used as programmable Counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.

• Low Power . . . 95 mW Typical Dissipation
• High Speed. . . 40 MHz Typical Count Frequency
• Synchronous Counting
• Asynchronous Master Reset and Parallel Load
• Individual Preset Inputs
• Cascading Circuitry Internally Provided
• Input Clamp Diodes Limit High Speed Termination Effects

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