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Part Name(s) : CXD2548R CXD2586R-1 CXD2586R/-1 Sony
Sony Semiconductor
Description : CD Digital Signal Processor with Built-in Digital Servo and DAC

Description
The CXD2586R/-1 is a digital signal processor LSI for CD players. This LSI incorporates the digital servo, digital filter and 1-bit DAC.

Features
• All digital signal processing during playback is performed with a single chip
• Highly integrated mounting possible due to a built-in RAM

Digital Signal Processor Block
• Playback mode which supports CAV (Constant
   Angular Velocity)
   • Frame jitter free
   • Half-speed to octuple-speed continuous playback
      possible with a low external clock (only CXD2586R-1
      supports up to octuple speed)
   • Allows relative rotational velocity readout
• Wide capture range playback mode
   • Spindle rotational velocity following method
   • Supports normal-speed, double-speed, quadruple
      speed, sextuple-speed and octuple-speed playback
      (only CXD2586R-1)
• Wide frame jitter margin (±28 frames) due to a
   built-in 32K RAM
• The bit clock, which strobes the EFM signal, is
   generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
   C1: double correction, C2: quadruple correction
• Octuple-speed (only CXD2586R-1), sextuple-speed,
   quadruple-speed and double-speed playback (digital
   signal processor and digital servo blocks)
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error detection
Digital spindle servo (with oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
   new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
Digital audio interface outputs
Digital level meter, peak meter
• Bilingual compatible

Digital Servo Block
• Microcomputer software-based flexible servo control
• Servo error signal, offset cancel function
• Servo loop, auto gain control function
• E:F balance, focus bias adjustment function

Digital Filters (DAC and LPF blocks)
• Low-pass filter for DAC
Digital de-emphasis
Digital attenuation
• 4fs oversampling filter
• Adopts secondary ∆∑ noise shaper
• LPF for DAC analog output

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Part Name(s) : CXD2598 CXD2598Q Sony
Sony Semiconductor
Description : CD Digital Signal Processor with Built-in Digital Servo and DAC

Description
The CXD2598Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, 1-bit DAC and analog low-pass filter on a single chip.

Features
• All digital signal processing during playback is performed with a single chip
• Highly integrated mounting possible due to a built in RAM

Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular Velocity)
  • Frame jitter free
  • 0.5×to 4×continuous playback possible
  • Allows relative rotational velocity readout
• Wide capture range playback mode
  • Spindle rotational velocity following method
  • Supports normal-speed to 4×speed playback
• Supports variable pitch playback
• The bit clock, which strobes the EFM signal, is generated by the digital PLL.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
  C1: double correction, C2: quadruple correction
  Supported during 4×speed playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub-Q data error detection
Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
Digital audio interface outputs
Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• CD TEXT data demodulation

Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages
  Focus filter: 5 stages

Digital Filter, DAC and Analog Low-Pass Filter Blocks
• DBB (digital bass boost) function
Digital de-emphasis
Digital attenuation
• 8fs oversampling digital filter
• Adoption of tertiary ∆∑noise shaper
• S/N: 100dB or more (master clock: 384Fs, typ.)
  Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384Fs, typ.)
• Rejection band attenuation: –60dB or less
• Double-speed playback supported

Applications
CD players

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Part Name(s) : CXD4016R Sony
Sony Semiconductor
Description : Transmission Digital Signal Processor IC for Infrared Spatial Digital Audio Communication

Description
The CXD4016R is an IC that processes the transmitted digital signals used for infrared spatial digital audio communication (based on the IEC61603-8-1 standard) in consumer products. This IC contains the digital-to-analog converter (DAC) and a PLL circuit for RF signal. RF signal is processed by digital signal processing, so the operation is stable without any adjustments.

Features
♦ Performs all the transmitted digital signal processing on a single chip
♦ Supports the infrared spatial digital audio communication system formats for consumer uses
♦ Support the three audio sampling frequencies (32kHz, 44.1kHz, 48kHz)
♦ Direct output of RF signals enabled by on-chip DAC
♦ External RAM and PLL circuit not required
< Audio I/F Block >
♦ Interfaces for various audio ADCs
< Parity Generator Block >
♦ Automatic generation of Reed-Solomon parity for the infrared spatial digital audio communication system format
< Modulator Block >
Digital processing throughout enables the transmitted RF signals in the infrared spatial digital audio communication system formats to be processed directly
♦ External analog circuit can be simplified by on-chip digital filter and on-chip DAC for RF signal applications
♦ Generation of subcarrier processed digitally
< Controller Block >
♦ Simple pin setting mode
♦ Serial interface provided by serial bus
< PLL Block >
♦ On-chip analog PLL circuit for generating the clock signals (640fs) required by the infrared spatial digital audio communication system formats

 

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Part Name(s) : PCM1795 PCM1795DB PCM1795DBR TI
Texas Instruments
Description : 32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog Converter

Description
The PCM1795 device is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters (DACs) and support circuitry in a small SSOP-28 package. The data converters use TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1795 provides balanced current outputs, letting the user optimize analog performance externally. The PCM1795 accepts pulse code modulation (PCM) and direct stream digital (DSD) audio data formats, thus providing an easy interface to audio digital signal processors (DSPs) and decoder chips. The PCM1795 device also interfaces with external digital filter devices such as the DF1704, DF1706, and the PMD200 from Pacific Microsonics™. Sampling rates up to 200 kHz are supported. A full set of user programmable functions is accessible through an SPI or I2C serial control port that supports register write and readback functions. The PCM1795 device also supports the time-division-multiplexed (TDM) command and audio (TDMCA) data format.

Features
• 32-Bit Resolution
• Analog Performance:
   – Dynamic Range: 123 dB
   – THD+N: 0.0005%
• Differential Current Output: 3.9 mAPP
• 8× Oversampling Digital Filter:
   – Stop-Band Attenuation: –98 dB
   – Passband Ripple: ±0.0002 dB
• Sampling Frequency: 10 kHz to 200 kHz
• System Clock: 128, 192, 256, 384, 512,
   or 768 fS With Autodetect
• Accepts 16-, 24-, and 32-Bit Audio Data
• PCM Data Formats: Standard, I2S, and Left
   Justified
• DSD Format Interface Available
• Interface Available for Optional External Digital
   Filter or DSP
• TDMCA or Serial Port (SPI™/I2C)
• User-Programmable Mode Controls:
   – Digital Attenuation:
      0 dB to –120 dB, 0.5-dB/Step
   – Digital De-Emphasis
   – Digital Filter Roll-Off: Sharp or Slow
   – Soft Mute
   – Zero Flag for Each Output
• Compatible With PCM1792A and PCM1796
   (Pins and Mode Controls)
• Dual Supply Operation:
   – 5-V Analog, 3.3-V Digital
• 5-V Tolerant Digital Inputs
• Small SSOP-28 Package

Applications
• A/V Receivers
• SACD Players
• DVD Players
• HDTV Receivers
• Car Audio Systems
Digital Multitrack Recorders
• Other Applications Requiring 32-Bit Audio

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Part Name(s) : DSD1608 DSD1608PAH DSD1608PAHR BB
Burr-Brown -> Texas Instruments
Description : 8-CHANNEL, ENHANCED MULTIFORMAT, DELTA-SIGMA, DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION
The DSD1608 is a CMOS, monolithic, 8-channel digital-to-analog converter which supports both PCM audio data format and direct stream digital (DSD) audio data format. The device includes an 8×digital interpolation filter and a digital DSD filter with three selectable frequency-response curves, followed by Texas Instruments’ enhanced multilevel delta-sigma modulator, which employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. Sampling rates up to 192 kHz for the PCM mode and 64 ×44.1 kHz for the DSD mode are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and read functions. The DSD1608 supports the time-division-multiplexed command and audio data (TDMCA) format. The DSD1608 is available in a 52-pin TQFP package.

FEATURES
 Supports DSD and PCM Formats
 Supports TDMCA
 Accepts 16-, 18-, 20- and 24-Bit Audio Data for PCM Format
 Analog Performance (VCC= 5 V):
  – Dynamic Range: 108 dB, Typical
  – SNR: 108 dB, Typical
  – THD+N: 0.0012%, Typical
  – Full-Scale Output: 4 Vpp, Typical
 Includes 8×Oversampling Digital Filter for PCM Format:
  – Stopband Attenuation: –60 dB
  – Passband Ripple: ±0.02 dB
 Includes Digital DSD FILTER for DSD Format:
  – Passband: 50 kHz, 70 kHz, 60 kHz at –3 dB  Sampling Frequency:
  – PCM Mode: 10 kHz to 200 kHz
  – DSD Mode: 64 ×44.1 kHz  System Clock:
  – 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS  Data Formats:
  – Standard, I2S, and Left-Justified for PCM Direct Stream Digital
 User-Programmable Mode Controls:
  – Digital Attenuation
  – Digital De-Emphasis
  – Digital Filter Rolloff: Sharp or Slow Soft Mute
  – Three Zero Flags
 Dual Supply Operation:
  – 5-V Analog, 3.3-V Digital 
Package: 52-Pin TQFP

APPLICATIONS
 Universal A/V Players
 SACD Players
 Car Audio Systems
 Other Applications Requiring 24-Bit Audio

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Part Name(s) : TLV320AIC3110 TLV320AIC3110IRHBR TLV320AIC3110IRHBT TI
Texas Instruments
Description : Low-Power Audio Codec With Audio Processing and Stereo Class-D Speaker Amplifier

Description
The TLV320AIC3110 device is a low-power, highly integrated, high-performance codec that supports stereo audio DAC, and mono audio ADC.
The TLV320AIC3110 device features a high-performance audio codec with 24-bit stereo playback and monaural record functionality. The device integrates several analog features, such as a microphone interface, headphone drivers, and speaker drivers. The digital-audio data format is programmable to work with popular audio standard protocols (I2S, left-justified and right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ is supported by the programmable digital-signal processing blocks (PRB). An on-chip PLL provides the high-speed clock required by the digital-signal processing block. The volume level is controlled either by pin control or by register control. The audio functions are controlled using the I2C serial bus.
The TLV320AIC3110 device has a programmable digital sine-wave generator and is available in a 32-pin VQFN package.

Features
• Stereo Audio DAC With 95-dB SNR
• Mono Audio ADC With 91-dB SNR
• Supports 8-kHz to 192-kHz Separate DAC and ADC Sample Rates
• Stereo 1.29-W Class-D BTL 8-Ω Speaker Driver With Direct Battery Connection
• One Differential and Three Single-Ended Inputs With Mixing and Level Controls
• Microphone With Bias, Preamp PGA, and AGC
• Built-in Digital Audio Processing Blocks (PRB) With User-Programmable Biquad, FIR Filters, and DRC
Digital Mixing Capability
• Programmable Digital Audio Processor for Bass Boost/Treble/EQ With up to Five Biquads for Record and up to Six Biquads for Playback
• Pin Control or Register Control for Digital-Playback Volume-Control Settings
Digital Sine-Wave Generator for Beeps and Key Clicks
• Integrated PLL Used for Programmable Digital Audio Processor
• I2S, Left-Justified, Right-Justified, DSP, and TDM Audio Interfaces
• I2C Control With Register Auto-Increment
• Full Power-Down Control
• Power Supplies:
   – Analog: 2.7 V–3.6 V
   – Digital Core: 1.65 V–1.95 V
   – Digital I/O: 1.1 V–3.6 V
   – Class-D: 2.7 V–5.5 V (SPLVDD and SPRVDD ≥ AVDD)
• 5-mm × 5-mm 32-VQFN Package

Applications
• Portable Audio Devices
• Mobile Internet Devices
• e-Books

 

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Part Name(s) : CXD2529Q Sony
Sony Semiconductor
Description : CD Digital Signal Processor

Description
The CXD2529Q is a digital signal processor LSI for CD players and is equipped with built-in digital filters, zero detection circuit, 1-bit DAC, and analog low pass filter on a single chip.

Features
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular Velocity)
   – Frame jitter-free
   – Allows 0.5 to double-speed continuous playback
   – Allows relative rotational velocity readout
   – Supports external spindle control
• Wide capture range mode
   – Spindle rotational velocity following method
   – Supports normal-speed and double-speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error detection
Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• Serial bus-based CPU interface
• Error correction monitor signals, etc. are output from a new CPU interface.
• Servo auto sequencer
Digital audio interface output
Digital peak meter

Digital Filter, DAC, Analog Low-Pass Filter Block
• DBB (Digital Bass Boost)
• Supports double-speed playback
Digital de-emphasis
Digital attenuation function
• Zero detection function
• 8fs oversampling digital filter
• S/N ratio: 100dB or more (master clock: 384fs typ.) Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384fs typ.)
• Rejection band attenuation: –60dB or more

Applications
  CD players

 

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Part Name(s) : 56F8000 56F8023 56F8033 MC56F8023 MC56F8023VLC MC56F8033 MC56F8033VLC MC56F8033/56F8023 MC56F8033/56F8023E Freescale
Freescale Semiconductor
Description : 16-bit Digital Signal Controllers

56F8033/56F8023 Description
The 56F8033/56F8023 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8033/56F8023 is well-suited for many applications. The 56F8033/56F8023 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general-purpose inverters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications.
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.

56F8033/56F8023 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• 56F8033 offers 64KB (32K x 16) Program Flash
• 56F8023 offers 32KB (16K x 16) Program Flash
• 56F8033 offers 8KB (4K x 16) Unified Data/Program RAM
• 56F8023 offers 4KB (2K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters (ADCs)
• Two Internal 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI) with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package

56F8033/56F8023 Features
Digital Signal Controller Core
• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging

Memory
• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
• On-chip memory— Master and slave modes
— Four-words-deep FIFOs available on both transmitter and receiver
— Programmable Length Transactions (2 to 16 bits)
• One Inter-Integrated Circuit (I2C) port
— Operates up to 400kbps
— Supports both master and slave operation
— Supports both 10-bit address mode and broadcasting mode
• One 16-bit Programmable Interval Timer (PIT)
• Two analog Comparators (CMPs)
— Selectable input source includes external pins, DACs
— Programmable output polarity
— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
• Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance
• Integrated Power-On Reset and Low-Voltage Interrupt Module
• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
• Clock sources:
— On-chip relaxation oscillator
— External clock: Crystal oscillator, ceramic resonator, and external clock source
• JTAG/EOnCE debug programming interface for real-time debugging
1.1.5 Energy Information
• Fabricated in high-density CMOS with 5V tolerance
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power

   — 64KB of Program Flash (56F80233 device)
     32KB of Program Flash (56F8023 device)
   — 8KB of Unified Data/Program RAM (56F8033 device)
     4KB of Unified Data/Program RAM (56F8023 device)
• EEPROM emulation capability using Flash

Peripheral Circuits for 56F8033/56F8023
• One multi-function six-output Pulse Width Modulator (PWM) module
   — Up to 96MHz PWM operating clock
   — 15 bits of resolution
   — Center-aligned and edge-aligned PWM signal mode
   — Four programmable fault inputs with programmable digital filter
   — Double-buffered PWM registers
   — Each complementary PWM signal pair allows selection of a PWM supply source from:
   – PWM generator
   – External GPIO
   – Internal timers
   – Analog comparator outputs
   – ADC conversion result which compares with values of ADC high- and low-limit registers to set PWM output
• Two independent 12-bit Analog-to-Digital Converters (ADCs)
   — 2 x 3 channel inputs
   — Supports both simultaneous and sequential conversions
   — ADC conversions can be synchronized by both PWM and timer modules
   — Sampling rate up to 2.67MSPS
   — 16-word result buffer registers
• Two internal 12-bit Digital-to-Analog Converters (DACs)
   — 2 μs settling time when output swing from rail to rail
   — Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and range
• One 16-bit multi-purpose Quad Timer module (TMR)
   — Up to 96MHz operating clock
   — Eight independent 16-bit counter/timers with cascading capability
   — Each timer has capture and compare capability
   — Up to 12 operating modes
• One Queued Serial Communication Interface (QSCI) with LIN Slave functionality
   — Full-duplex or single-wire operation
   — Two receiver wake-up methods:
   – Idle line
   – Address mark
   — Four-bytes-deep FIFOs are available on both transmitter and receiver
• One Queued Serial Peripheral Interfaces (QSPI)
   — Full-duplex operation
   — Master and slave modes
   — Four-words-deep FIFOs available on both transmitter and receiver
   — Programmable Length Transactions (2 to 16 bits)
• One Inter-Integrated Circuit (I2C) port
   — Operates up to 400kbps
   — Supports both master and slave operation
   — Supports both 10-bit address mode and broadcasting mode
• One 16-bit Programmable Interval Timer (PIT)
• Two analog Comparators (CMPs)
   — Selectable input source includes external pins, DACs
   — Programmable output polarity
   — Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
   — Output falling and rising edge detection able to generate interrupts
• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
• Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance
• Integrated Power-On Reset and Low-Voltage Interrupt Module
• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
• Clock sources:
   — On-chip relaxation oscillator
   — External clock: Crystal oscillator, ceramic resonator, and external clock source
• JTAG/EOnCE debug programming interface for real-time debugging

Energy Information
• Fabricated in high-density CMOS with 5V tolerance
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power

 

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Part Name(s) : PTD08A020W PTD08A020WAD TI
Texas Instruments
Description : 20-A, 4.75-V to 14-V INPUT, NON-ISOLATED, WIDE-OUTPUT, DIGITAL POWERTRAIN™ MODULE

DESCRIPTION
The PTD08A020W is a high-performance 20-A rated, non-isolated digital PowerTrain module. This module is the power conversion section of a digital power system which incorporates TIs UCD7230 MOSFET driver IC. The PTD08A020W must be used in conjunction with a digital power controller such as the UCD9240 or UCD9110 family. The PTD08A020W receives control signals from the digital controller and provides parametric and status information back to the digital controller. Together, PowerTrain modules and a digital power controller form a sophisticated, robust, and easily configured power management solution.
Operating from an input voltage range of 4.75 V to 14 V, the PTD08A020W provides step-down power conversion to a wide range of output voltages from, 0.7 V to 3.6 V. The wide input voltage range makes the PTD08A020W particularly suitable for advanced computing and server applications that utilize a loosely regulated 8-V, 9.6-V or 12-V intermediate distribution bus. Additionally, the wide input voltage range increases design flexibility by supporting operation with tightly regulated 5-V or 12-V intermediate bus architectures.
The module incorporates output over-current and temperature monitoring which protects against most load faults. Output current and module temperature signals are provided for the digital controller to permit user defined over-current and over-temperature warning and fault scerarios.
The module uses double-sided surface mount construction to provide a low profile and compact footprint. Package options include both through-hole and surface mount configurations that are lead (Pb) - free and RoHS compatible.

FEATURES
• Up to 20-A Output Current
• 4.75-V to 14-V Input Voltage
• Programmable Wide-Output Voltage
   (0.7 V to 3.6 V)
• Efficiencies up to 96%
Digital I/O
   – PWM signal
   – INHIBIT
   – Current limit flag (FAULT)
   – Sychronous Rectifier Enable (SRE)
• Analog I/O
   – Temperature
   – Output currrent
• Safety Agency Approvals: (Pending)
   – UL/IEC/CSA-C22.2 60950-1
• Operating Temperature: –40°C to 85°C

APPLICATIONS
Digital Power Systems
   using UCD92XX Digital Controllers

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Part Name(s) : DSD1792 DSD1792DB DSD1792DBR BB
Burr-Brown -> Texas Instruments
Description : 24-BIT, 192-KHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION
The DSD1792 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1792 provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1792 accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1792 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user−programmable functions is accessible through a 4-wire serial control port, which supports register write and readback functions. The DSD1792 also supports the time-division-multiplexed command and audio (TDMCA) data format.

FEATURES
● Supports Both DSD and PCM Formats
● 24-Bit Resolution
● Analog Performance:
   − Dynamic Range:
   − 132 dB (9 V rms, Mono)
   − 129 dB (4.5 V rms, Stereo)
   − 127 dB (2 V rms, Stereo)
   − THD+N: 0.0004%
● Differential Current Output: 7.8 mA p-p
● 8× Oversampling Digital Filter:
   − Stop-Band Attenuation: –130 dB
   − Pass-Band Ripple: ±0.00001 dB
● Sampling Frequency: 10 kHz to 200 kHz
● System Clock: 128, 192, 256, 384, 512, or 768 fS With Autodetect
● Accepts 16-, 20-, and 24-Bit Audio Data
● PCM Data Formats: Standard, I2S, and Left-Justified
● Optional Interface to External Digital Filter or DSP Available
● TDMCA Interface Available
● User-Programmable Mode Controls:
   − Digital Attenuation: 0 dB to –120 dB, 0.5 dB/Step
   − Digital De-Emphasis
   − Digital Filter Rolloff: Sharp or Slow
   − Soft Mute
● Dual Supply Operation:
   − 5 V Analog, 3.3 V Digital
● 5-V Tolerant Digital Inputs
● Small 28-Lead SSOP Package, Lead-Free Product

APPLICATIONS
● A/V Receivers
● SACD Player
● DVD Players
● HDTV Receivers
● Car Audio Systems
Digital Multi-Track Recorders
● Other Applications Requiring 24-Bit Audio

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