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74LVQ10

  

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74LVQ10_2004[TRIPLE 3-INPUT NAND GATE]

other part :74LVQ10MTR_2004   74LVQ10TTR_2004  

DESCRIPTION
The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.3ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 2µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY

STMicroelectronics
ST-Microelectronics

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74LVQ10[TRIPLE 3-INPUT NAND GATE]

other part :74LVQ10M   74LVQ10MTR   74LVQ10TTR  

DESCRIPTION
The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.3ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 2µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY

STMicroelectronics
ST-Microelectronics

View

74LVQ10M[TRIPLE 3-INPUT NAND GATE]

other part :74LVQ10   74LVQ10MTR   74LVQ10TTR  

DESCRIPTION
The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.3ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 2µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY

STMicroelectronics
ST-Microelectronics

View

74LVQ10MTR_2004[TRIPLE 3-INPUT NAND GATE]

other part :74LVQ10_2004   74LVQ10TTR_2004  

DESCRIPTION
The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.3ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 2µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY

STMicroelectronics
ST-Microelectronics

View

74LVQ10MTR[TRIPLE 3-INPUT NAND GATE]

other part :74LVQ10   74LVQ10M   74LVQ10TTR  

DESCRIPTION
The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.3ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 2µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY

STMicroelectronics
ST-Microelectronics

View

74LVQ10TTR_2004[TRIPLE 3-INPUT NAND GATE]

other part :74LVQ10_2004   74LVQ10MTR_2004  

DESCRIPTION
The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.3ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 2µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY

STMicroelectronics
ST-Microelectronics

View

74LVQ10TTR[TRIPLE 3-INPUT NAND GATE]

other part :74LVQ10   74LVQ10M   74LVQ10MTR  

DESCRIPTION
The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.3ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 2µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY

STMicroelectronics
ST-Microelectronics

View
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