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74LVQ138M

  

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74LVQ138M[3 TO 8 LINE DECODER (INVERTING)]

other part :74LVQ138   74LVQ138MTR   74LVQ138TTR  

DESCRIPTION
The 74LVQ138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
   
■ HIGH SPEED:
    tPD = 5.5ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
    ICC = 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
    VOLP = 0.2V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING
    CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
    |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:
    tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
    VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
    74 SERIES 138
■ IMPROVED LATCH-UP IMMUNITY
   

STMicroelectronics
ST-Microelectronics

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74LVQ138MTR_2004[3 TO 8 LINE DECODER (INVERTING)]

other part :74LVQ138_2004   74LVQ138TTR_2004  

DESCRIPTION
The 74LVQ138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
   
■ HIGH SPEED:
    tPD = 5.5ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
    ICC = 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
    VOLP = 0.2V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING
    CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
    |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:
    tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
    VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
    74 SERIES 138
■ IMPROVED LATCH-UP IMMUNITY
   

STMicroelectronics
ST-Microelectronics

View

74LVQ138MTR[3 TO 8 LINE DECODER (INVERTING)]

other part :74LVQ138   74LVQ138M   74LVQ138TTR  

DESCRIPTION
The 74LVQ138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
   
■ HIGH SPEED:
    tPD = 5.5ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
    ICC = 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
    VOLP = 0.2V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING
    CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
    |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:
    tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
    VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
    74 SERIES 138
■ IMPROVED LATCH-UP IMMUNITY
   

STMicroelectronics
ST-Microelectronics

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