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74VHCT373A

  

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Match, Like 74VHCT373A 74VHCT373AM 74VHCT373AN 74VHCT373AT
Start with 74VHCT373AC* 74VHCT373AM* 74VHCT373AN* 74VHCT373AS* 74VHCT373AT* 74VHCT373A_*
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Included *74VHCT373AD*

74VHCT373A_1999[Octal D-Type Latch with 3-STATE Outputs]

other part :74VHCT373AM_1999   74VHCT373AN_1999   74VHCT373ASJ_1999   74VHCT373AMX_1999   74VHCT373AMTC_1999   74VHCT373ASJX_1999   74VHCT373AMTCX_1999  

General Description
The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

Features
■ High speed: tPD = 7.7 ns (typ) at TA = 25°C
■ High Noise Immunity: VIH = 2.0V, VIL = 0.8V
■ Power Down Protection is provided on all inputs and outputs
■ Low Power Dissipation:
   ICC = 4 µA (max) @ TA = 25°C
■ Pin and Function Compatible with 74HCT373

Fairchild Semiconductor
Fairchild

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74VHCT373A[Octal D-Type Latch with 3-STATE Outputs]

other part :74VHCT373AM   74VHCT373AN   74VHCT373ASJ   74VHCT373AMX   74VHCT373AMTC   74VHCT373ASJX   74VHCT373AMTCX  

General Description
The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

Features
■ High speed: tPD 7.7 ns (typ) at TA 25°C
■ High Noise Immunity: VIH 2.0V, VIL 0.8V
■ Power Down Protection is provided on all inputs and outputs
■ Low Power Dissipation:
   ICC 4 μA (max) @ TA 25°C
■ Pin and Function Compatible with 74HCT373

Fairchild Semiconductor
Fairchild

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74VHCT373A_2001[OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING]

other part :74VHCT373AM_2001   74VHCT373AMTR_2001   74VHCT373ATTR_2001  

DESCRIPTION
The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS:
   VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN PROTECTION ON INPUTS & OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V (MAX.)

STMicroelectronics
ST-Microelectronics

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74VHCT373A[OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING]

other part :74VHCT373AMTR   74VHCT373ATTR  

DESCRIPTION
The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS:
   VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN PROTECTION ON INPUTS & OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V (MAX.)

STMicroelectronics
ST-Microelectronics

View

74VHCT373AM[OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING]

other part :74VHCT373AT   74VHCT373A_99  

DESCRIPTION
The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q outputs will follow the data inputs precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ COMPATIBLEWITH TTL OUTPUTS:
   VIH = 2V (MIN), VIL = 0.8V(MAX)
■ POWERDOWN PROTECTIONON INPUTS & OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V(Max.)

STMicroelectronics
ST-Microelectronics

View

74VHCT373AM_1999[Octal D-Type Latch with 3-STATE Outputs]

other part :74VHCT373A_1999   74VHCT373AN_1999   74VHCT373ASJ_1999   74VHCT373AMX_1999   74VHCT373AMTC_1999   74VHCT373ASJX_1999   74VHCT373AMTCX_1999  

General Description
The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

Features
■ High speed: tPD = 7.7 ns (typ) at TA = 25°C
■ High Noise Immunity: VIH = 2.0V, VIL = 0.8V
■ Power Down Protection is provided on all inputs and outputs
■ Low Power Dissipation:
   ICC = 4 µA (max) @ TA = 25°C
■ Pin and Function Compatible with 74HCT373

Fairchild Semiconductor
Fairchild

View

74VHCT373AM[Octal D-Type Latch with 3-STATE Outputs]

other part :74VHCT373A   74VHCT373AN   74VHCT373ASJ   74VHCT373AMX   74VHCT373AMTC   74VHCT373ASJX   74VHCT373AMTCX  

General Description
The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

Features
■ High speed: tPD 7.7 ns (typ) at TA 25°C
■ High Noise Immunity: VIH 2.0V, VIL 0.8V
■ Power Down Protection is provided on all inputs and outputs
■ Low Power Dissipation:
   ICC 4 μA (max) @ TA 25°C
■ Pin and Function Compatible with 74HCT373

Fairchild Semiconductor
Fairchild

View

74VHCT373AM_2001[OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING]

other part :74VHCT373A_2001   74VHCT373AMTR_2001   74VHCT373ATTR_2001  

DESCRIPTION
The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS:
   VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN PROTECTION ON INPUTS & OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V (MAX.)

STMicroelectronics
ST-Microelectronics

View

74VHCT373AN_1999[Octal D-Type Latch with 3-STATE Outputs]

other part :74VHCT373A_1999   74VHCT373AM_1999   74VHCT373ASJ_1999   74VHCT373AMX_1999   74VHCT373AMTC_1999   74VHCT373ASJX_1999   74VHCT373AMTCX_1999  

General Description
The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

Features
■ High speed: tPD = 7.7 ns (typ) at TA = 25°C
■ High Noise Immunity: VIH = 2.0V, VIL = 0.8V
■ Power Down Protection is provided on all inputs and outputs
■ Low Power Dissipation:
   ICC = 4 µA (max) @ TA = 25°C
■ Pin and Function Compatible with 74HCT373

Fairchild Semiconductor
Fairchild

View

74VHCT373AN[Octal D-Type Latch with 3-STATE Outputs]

other part :74VHCT373A   74VHCT373AM   74VHCT373ASJ   74VHCT373AMX   74VHCT373AMTC   74VHCT373ASJX   74VHCT373AMTCX  

General Description
The VHCT373A is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. When the OE input is HIGH, the eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

Features
■ High speed: tPD 7.7 ns (typ) at TA 25°C
■ High Noise Immunity: VIH 2.0V, VIL 0.8V
■ Power Down Protection is provided on all inputs and outputs
■ Low Power Dissipation:
   ICC 4 μA (max) @ TA 25°C
■ Pin and Function Compatible with 74HCT373

Fairchild Semiconductor
Fairchild

View
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