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74VHCT573AMTR

  

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74VHCT573AMTR_2000[OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING]

other part :74VHCT573A_2000   74VHCT573AM_2000   74VHCT573ATTR_2000  

DESCRIPTION
The 74VHCT573A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-type latch are controlled by a latch enable input (LE) and an output enable input (OE). When the LE inputs is held at a high level, the Q outputs will follow the data input precisely . When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5.4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS:
   VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN PROTECTION ON INPUTS & OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V (MAX.)

STMicroelectronics
ST-Microelectronics

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74VHCT573AMTR[OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING]

other part :74VHCT573A   74VHCT573AM   74VHCT573ATTR  

DESCRIPTION
The 74VHCT573A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-type latch are controlled by a latch enable input (LE) and an output enable input (OE). When the LE inputs is held at a high level, the Q outputs will follow the data input precisely . When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5.4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS:
   VIH = 2V (MIN.), VIL = 0.8V (MAX)
■ POWER DOWN PROTECTION ON INPUTS & OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V (MAX.)

STMicroelectronics
ST-Microelectronics

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