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MBM29DL164BE

  

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MBM29DL164BE[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL161BE   MBM29DL161BE-70PBT   MBM29DL161BE-70TN   MBM29DL161BE-70TR   MBM29DL161BE-90PBT   MBM29DL161BE-90TN   MBM29DL161BE-90TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE12TN[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL163TE-12PN   MBM29DL163TE-70PN   MBM29DL161TE-12TN   MBM29DL161TE-12TR   MBM29DL161TE-12PBT   MBM29DL161BE-12TN   MBM29DL161BE-12TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE90TR[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL161BE   MBM29DL161BE-70PBT   MBM29DL161BE-70TN   MBM29DL161BE-70TR   MBM29DL161BE-90PBT   MBM29DL161BE-90TN   MBM29DL161BE-90TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE70TN[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL161BE   MBM29DL161BE-70PBT   MBM29DL161BE-70TN   MBM29DL161BE-70TR   MBM29DL161BE-90PBT   MBM29DL161BE-90TN   MBM29DL161BE-90TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE12TR[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL163TE-12PN   MBM29DL163TE-70PN   MBM29DL161TE-12TN   MBM29DL161TE-12TR   MBM29DL161TE-12PBT   MBM29DL161BE-12TN   MBM29DL161BE-12TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE90TN[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL161BE   MBM29DL161BE-70PBT   MBM29DL161BE-70TN   MBM29DL161BE-70TR   MBM29DL161BE-90PBT   MBM29DL161BE-90TN   MBM29DL161BE-90TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE70TR[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL161BE   MBM29DL161BE-70PBT   MBM29DL161BE-70TN   MBM29DL161BE-70TR   MBM29DL161BE-90PBT   MBM29DL161BE-90TN   MBM29DL161BE-90TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE-12TN[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL163TE-12PN   MBM29DL163TE-70PN   MBM29DL161TE-12TN   MBM29DL161TE-12TR   MBM29DL161TE-12PBT   MBM29DL161BE-12TN   MBM29DL161BE-12TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

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MBM29DL164BE-90TR[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL161BE   MBM29DL161BE-70PBT   MBM29DL161BE-70TN   MBM29DL161BE-70TR   MBM29DL161BE-90PBT   MBM29DL161BE-90TN   MBM29DL161BE-90TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View

MBM29DL164BE90PBT[FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation]

other part :MBM29DL161BE   MBM29DL161BE-70PBT   MBM29DL161BE-70TN   MBM29DL161BE-70TR   MBM29DL161BE-90PBT   MBM29DL161BE-90TN   MBM29DL161BE-90TR  

■ GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.

■ FEATURES
• 0.23 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes
   (Refer to “MBM29DL16XTE/BE Device Bank Divisions Table” in ■GENERAL DESCRIPTION)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(1) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)
   48-pin FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Eight 4K word and thirty one 32K word sectors in word mode
   Eight 8K byte and thirty one 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• HiddenROM region
   64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Program Suspend/Resume
   Suspends the program operation to allow a read in another sector with in the same device
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Fujitsu
Fujitsu

View
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