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MC74HC73

  

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MC74HC73[Dual J-K Flip-Flop with Reset]

other part :MC74HC73N   MC74HC73D  

Dual J-K Flip-Flop with Reset
High–Performance Silicon–Gate CMOS

The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip flop is negative–edge clocked and has an active–low asynchronous reset.
The MC74HC73 is identical in function to the HC107, but has a different pinout.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 92 FETs or 23 Equivalent Gates

Motorola => Freescale
Motorola

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MC74HC73A[Dual J-K Flip-Flop with Reset]

other part :MC74HC73ADG   MC74HC73ADR2G   NLV74HC73ADR2G   MC74HC73ADTG   MC74HC73ADTR2G  

Dual J-K Flip-Flop with Reset
High−Performance Silicon−Gate CMOS

The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a different pinout.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 92 FETs or 23 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These are Pb−Free Devices

ON Semiconductor
ON-Semiconductor

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MC74HC73D[Dual J-K Flip-Flop with Reset]

other part :MC74HC73   MC74HC73N  

Dual J-K Flip-Flop with Reset
High–Performance Silicon–Gate CMOS

The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip flop is negative–edge clocked and has an active–low asynchronous reset.
The MC74HC73 is identical in function to the HC107, but has a different pinout.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 92 FETs or 23 Equivalent Gates

Motorola => Freescale
Motorola

View

MC74HC73N[Dual J-K Flip-Flop with Reset]

other part :MC74HC73   MC74HC73D  

Dual J-K Flip-Flop with Reset
High–Performance Silicon–Gate CMOS

The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip flop is negative–edge clocked and has an active–low asynchronous reset.
The MC74HC73 is identical in function to the HC107, but has a different pinout.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 92 FETs or 23 Equivalent Gates

Motorola => Freescale
Motorola

View

MC74HC73ADG[Dual J-K Flip-Flop with Reset]

other part :MC74HC73A   MC74HC73ADR2G   NLV74HC73ADR2G   MC74HC73ADTG   MC74HC73ADTR2G  

Dual J-K Flip-Flop with Reset
High−Performance Silicon−Gate CMOS

The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a different pinout.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 92 FETs or 23 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These are Pb−Free Devices

ON Semiconductor
ON-Semiconductor

View

MC74HC73ANG[Dual J-K Flip-Flop with Reset]

Dual J-K Flip-Flop with Reset
High−Performance Silicon−Gate CMOS

The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a different pinout.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 92 FETs or 23 Equivalent Gates
• These are Pb−Free Devices

ON Semiconductor
ON-Semiconductor

View

MC74HC73ADTG[Dual J-K Flip-Flop with Reset]

other part :MC74HC73A   MC74HC73ADG   MC74HC73ADR2G   NLV74HC73ADR2G   MC74HC73ADTR2G  

Dual J-K Flip-Flop with Reset
High−Performance Silicon−Gate CMOS

The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a different pinout.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 92 FETs or 23 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These are Pb−Free Devices

ON Semiconductor
ON-Semiconductor

View

MC74HC73ADR2G[Dual J-K Flip-Flop with Reset]

other part :MC74HC73A   MC74HC73ADG   NLV74HC73ADR2G   MC74HC73ADTG   MC74HC73ADTR2G  

Dual J-K Flip-Flop with Reset
High−Performance Silicon−Gate CMOS

The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a different pinout.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 92 FETs or 23 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These are Pb−Free Devices

ON Semiconductor
ON-Semiconductor

View

MC74HC73ADTR2G[Dual J-K Flip-Flop with Reset]

other part :MC74HC73A   MC74HC73ADG   MC74HC73ADR2G   NLV74HC73ADR2G   MC74HC73ADTG  

Dual J-K Flip-Flop with Reset
High−Performance Silicon−Gate CMOS

The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a different pinout.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 92 FETs or 23 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These are Pb−Free Devices

ON Semiconductor
ON-Semiconductor

View
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