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CD74HCT73

  

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CD74HCT73[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :CD54HC73   CD74HC73   CD54HC73F   CD74HC73E   CD74HC73M   CD74HCT73M   CD74HCT73E  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
TI

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CD74HCT73[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :HC73M   HCT73M   CD54HC73   CD74HC73   CD74HC73M   CD74HC73E   CD54HC73F  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
Texas-Instruments

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CD74HCT73E[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :CD54HC73   CD74HC73   CD54HC73F   CD74HC73E   CD74HC73M   CD74HCT73   CD74HCT73M  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
TI

View

CD74HCT73E[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :HC73M   HCT73M   CD54HC73   CD74HC73   CD54HC73F   CD74HC73M   CD74HC73E  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
Texas-Instruments

View

CD74HCT73M[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :CD54HC73   CD74HC73   CD54HC73F   CD74HC73E   CD74HC73M   CD74HCT73   CD74HCT73E  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
TI

View

CD74HCT73M[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :HC73M   HCT73M   CD54HC73   CD74HC73   CD74HC73E   CD74HC73M   CD74HCT73  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
Texas-Instruments

View

CD74HCT73EE4[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :CD54HC73   CD74HC73   CD54HC73F   CD74HC73E   CD74HC73M   CD74HCT73   CD74HCT73M  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
TI

View

CD74HCT73EE4[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :HC73M   HCT73M   CD54HC73   CD74HC73   CD54HC73F   CD74HC73M   CD74HC73E  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
Texas-Instruments

View

CD74HCT73ME4[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :CD54HC73   CD74HC73   CD54HC73F   CD74HC73E   CD74HC73M   CD74HCT73   CD74HCT73M  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
TI

View

CD74HCT73MG4[Dual J-K Flip-Flop with Reset Negative-Edge Trigger]

other part :CD54HC73   CD74HC73   CD54HC73F   CD74HC73E   CD74HC73M   CD74HCT73   CD74HCT73M  

Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
   
Features
• Hysteresis on Clock Inputs for Improved Noise
    Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
    TA = 25°C
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
    Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
        at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility,
        VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
   

Texas Instruments
TI

View
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