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AD16M324RCD-5[Low voltage operation is more suitable to be used on battery backup, portable electronic]

other part :AD4016M41VCA-5   AD4016M41VCB-5   AD4016M41VCC-5   AD4016M41VCD-5   AD4016M41VTA-5   AD4016M41VTB-5   AD4016M41VTC-5  

[ASCEND Semiconductor]

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Unspecified
ETC

View

EP3C120M324A6ES[Cyclone III Device Handbook]

other part :EP3C10   EP3C10E144A6ES   EP3C10E144A6N   EP3C10E144A7ES   EP3C10E144A7N   EP3C10E144A8ES   EP3C10E144A8N  

Cyclone III Device Family Overview
Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost
■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.

This chapter contains the following sections:
■ “Cyclone III Device Family Features” on page 1–1
■ “Cyclone III Device Family Architecture” on page 1–6
■ “Reference and Ordering Information” on page 1–12

Altera Corporation
Altera

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AD4M324VCB-5[Low voltage operation is more suitable to be used on battery backup, portable electronic]

other part :AD4016M41VCA-5   AD4016M41VCB-5   AD4016M41VCC-5   AD4016M41VCD-5   AD4016M41VTA-5   AD4016M41VTB-5   AD4016M41VTC-5  

[ASCEND Semiconductor]

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Unspecified
ETC

View

EP3C80M324I8ES[Cyclone III Device Handbook]

other part :EP3C10   EP3C10E144A6ES   EP3C10E144A6N   EP3C10E144A7ES   EP3C10E144A7N   EP3C10E144A8ES   EP3C10E144A8N  

Cyclone III Device Family Overview
Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost
■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.

This chapter contains the following sections:
■ “Cyclone III Device Family Features” on page 1–1
■ “Cyclone III Device Family Architecture” on page 1–6
■ “Reference and Ordering Information” on page 1–12

Altera Corporation
Altera

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HYM324020S[4M x 32-Bit Dynamic RAM Module]

other part :HYM324020GS   HYM324020GS-50   HYM324020GS-60   HYM324020S-50   HYM324020S-60   HYM324020S-GS50   Q67100-Q2005  

The HYM 324020S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by 32-bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRAMs in 300 mil wide SOJ-packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a PC board.
The HYM 324020S/GS-50/-60 can also be used as a 8 388 608 words by 16-bits dynamic RAM module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, …, DQ15 and DQ31, respectively.
Each HYB 5117400BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324020S/GS-50/-60 dictates the use of early write cycles.

Advanced Information
• 4 194 304 words by 32-bit organization (alternative 8 388 608 words by 16-bit)
• Fast access and cycle time
   50 ns access time
   90 ns cycle time (-50 version)
   60 ns access time
   110 ns cycle time (-60 version)
• Fast page mode capability
   35 ns cycle time (-50 version)
   40 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
   max. 5280 mW active (HYM 324020S/GS-50)
   max. 4840 mW active (HYM 324020S/GS-60)
   CMOS – 44 mW standby
   TTL –88 mW standby
• CAS-before-RAS refresh
   RAS-only-refresh
   Hidden-refresh
• 8 decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module with 22.86 mm (900 mil) height
• Utilizes eight 4Mx4-DRAMs in 300mil wide SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write non-parity applications
• Tin-Lead contact pads (S - version)
• Gold contact pads (GS - version)

 

Siemens AG
Siemens

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AD404M324RSD-5[Low voltage operation is more suitable to be used on battery backup, portable electronic]

other part :AD4016M41VCA-5   AD4016M41VCB-5   AD4016M41VCC-5   AD4016M41VCD-5   AD4016M41VTA-5   AD4016M41VTB-5   AD4016M41VTC-5  

[ASCEND Semiconductor]

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Unspecified
ETC

View

EP3C25M324C8ES[Cyclone III Device Handbook]

other part :EP3C10   EP3C10E144A6ES   EP3C10E144A6N   EP3C10E144A7ES   EP3C10E144A7N   EP3C10E144A8ES   EP3C10E144A8N  

Cyclone III Device Family Overview
Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost
■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.

This chapter contains the following sections:
■ “Cyclone III Device Family Features” on page 1–1
■ “Cyclone III Device Family Architecture” on page 1–6
■ “Reference and Ordering Information” on page 1–12

Altera Corporation
Altera

View

AD16M324VTB-5[Low voltage operation is more suitable to be used on battery backup, portable electronic]

other part :AD4016M41VCA-5   AD4016M41VCB-5   AD4016M41VCC-5   AD4016M41VCD-5   AD4016M41VTA-5   AD4016M41VTB-5   AD4016M41VTC-5  

[ASCEND Semiconductor]

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Unspecified
ETC

View

AD4M324VSB-5[Low voltage operation is more suitable to be used on battery backup, portable electronic]

other part :AD4016M41VCA-5   AD4016M41VCB-5   AD4016M41VCC-5   AD4016M41VCD-5   AD4016M41VTA-5   AD4016M41VTB-5   AD4016M41VTC-5  

[ASCEND Semiconductor]

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Unspecified
ETC

View

AD8M324RPA-5[Low voltage operation is more suitable to be used on battery backup, portable electronic]

other part :AD4016M41VCA-5   AD4016M41VCB-5   AD4016M41VCC-5   AD4016M41VCD-5   AD4016M41VTA-5   AD4016M41VTB-5   AD4016M41VTC-5  

[ASCEND Semiconductor]

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Unspecified
ETC

View
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