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AM85C30 Datasheet PDF - Advanced Micro Devices

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Advanced Micro Devices AMD
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AMD’s Am85C30 is an enhanced pin-compatible version of the popular Am8530H Serial Communications Controller. The Enhanced Serial Communications Controller (ESCC) is a high-speed, low-power, multiprotocol communications peripheral designed for use with 8- and 16-bit microprocessors. It has two independent,full-duplex channels and functions as a serial-toparallel, parallel-to-serial converter/controller. AMD’s proprietary enhancements make the Am85C30 easier to interface and more effective in high-speed applications due to a reduction in software burden and the elimination of the need for some external glue logic.

■ Fastest data rate of any Am8530
   — 8.192 MHz / 2.048 Mb/s
   — 10 MHz / 2.5 Mb/s
   — 16.384 MHz / 4.096 Mb/s
■ Low-power CMOS technology
■ Pin and function compatible with other NMOS and CMOS 8530s
■ Easily interfaced with most CPUs
   — Compatible with non-multiplexed bus
■ Many enhancements over NMOS Am8530H
   — Allows Am85C30 to be used more effectively in high-speed applications
   — Improves interface capabilities
■ Two independent full-duplex serial channels
■ Asynchronous mode features
   — Programmable stop bits, clock factor, character length and parity
   — Break detection/generation
   — Error detection for framing, overrun, and parity
■ Synchronous mode features
   — Supports IBM® BISYNC, SDLC, SDLC Loop, HDLC, and ADCCP Protocols
   — Programmable CRC generators and checkers
   — SDLC/HDLC support includes frame control, zero insertion and deletion, abort, and residue handling
■ Enhanced SCC functions support high-speed frame reception using DMA
   — 14-bit byte counter
   — 10 × 19 SDLC/HDLC Frame Status FIFO
   — Independent Control on both channels
   — Enhanced operation does not allow special receive conditions to lock the 3-byte DATA FIFO when the 10 × 19 FIFO is enabled
■ Local Loopback and Auto Echo modes
■ Internal or external character synchronization
■ 2-Mb/s FM encoding transmit and receive capability using internal DPLL for 16.384-MHz product
■ Internal synchronization between RxC to PCLK and TxC to PCLK
   — This allows the user to eliminate external synchronization hardware required by the NMOS device when transmitting or receiving data at the maximum rate of 1/4 PCLK frequency


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