Description
The FS612510 is a low skew, low jitter CMOS zero-delay phase-lock loop (PLL) clock buffer IC designed for highspeed motherboard applications, such as those using 133MHz SDRAM.

Features
• Generates one bank of ten clock outputs (1Y0 to 1Y9) from one reference clock input (CLK)
• Designed to meet the PLL Component Specifications as noted in the PC133 SDRAM Registered DIMM Design Specification
• External feedback input (FBIN) to synchronize all clock outputs to the reference input
• Operating frequency 25MHz to 140MHz
• Tight tracking skew (spread-spectrum tolerant)
• On-chip 25Ω series damping resistors for driving point-to-point loads
• Output enable (G) enables or disables low all clock outputs
• Available with an auto power-down option that turns off the PLL and forces all outputs low when the reference clock stops (FS612510-02)
• Packaged in a 24-pin TSSOP