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FIN1025

  

Datasheet PDF - Fairchild Semiconductor

FIN1025 image

Part Name
FIN1025

Other PDF
  no available.

PDF

page
7 Pages

File Size
262.8 kB

MFG CO.
Fairchild
Fairchild Semiconductor 

General Description
This dual driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350mV which provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data.
The FIN1025 can be paired with its companion receiver, the FIN1026, or any other LVDS receiver.
   
Features
■ Greater than 400Mbs data rate
■ Flow-through pinout simplifies PCB layout
■ 3.3V power supply operation
■ 0.4ns maximum differential pulse skew
■ 1.7ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ 14-Lead TSSOP package saves space
   


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