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Music-Semiconductors
Music Semiconductors
Description : AltoPriority Queue Scheduler

General Description
The MUPA64K16 Alto Priority Queue Scheduler is a high-performance sorting engine designed to support packet scheduling in high-speed switch or router applications. Alto can support any scheduling algorithm for which a Priority Queue is required, such as Weighted Fair Queuing, Start-Time Fair Queuing and Self-Clocked Fair Queuing.

Features
Priority Queue with insert, extract and peek operations
• Packet processing time of 150 ns
• 65,536 Priority Queue entries
• 32-bit sorting key
• 16-bit associated data value
• Supports up to 65,536 FIFO Queues
• Supports up to 16 physical switch ports
• Wrap register per port handles counter rollover
• UID Manager generates unique associated data values
• 32-bit synchronous data interface
• 17-bit SRAM address bus
• 15 ns clock
• 1.8V core / 3.3V I/O
• 128-pin LQFP package (14 x 20 mm)
• Industrial Temperature grade available
• IEEE 1149.1 JTAG boundary scan logic

Philips
Philips Electronics
Description : 8-input Priority encoder

DESCRIPTION
The 74F148 8-input Priority encoder accepts data from eight active-Low inputs and provides a binary representation on the three active-Low outputs. A Priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest Priority is represented on the output, with input line I7 having the highest Priority.

FEATURES
•Code conversions
•Multi-channel D/A converter
•Decimal-to-BCD converter
•Cascading for Priority encoding of “N” bits
•Input enable capability
Priority encoding-automatic selection of highest Priority input line
•Output enable-active Low when all inputs are High
•Group signal output-active when any input is Low

Motorola
Motorola => Freescale
Description : 8-line to 3-line Priority encoder

8-LINE TO 3-LINE Priority ENCODER FAST™ SHOTTKY TTL

The MC54/74F148 provides three bits of binary coded output representing the position of the highest order active input, along with an output indicating thepresence of anyactive input. It is easily expanded via input and output enables to provide Priority encoding over many bits.


• Encodes Eight Data Lines in Priority
• Provides 3-Bit Binary Priority Code
• Input Enable Capability
• Signals When Data Present on Any Input
• Cascadable for Priority Encoding of n Bits

Fairchild
Fairchild Semiconductor
Description : 8-Line to 3-Line Priority Encoder

General Description
The F148 provides three bits of binary coded output repre senting the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide Priority encoding over many bits.

Features
■ Encodes eight data lines in Priority
■ Provides 3-bit binary Priority code
■ Input enable capability
■ Signals when data is present on any input
■ Cascadable for Priority encoding of n bits

Part Name(s) : 74F148CW
Fairchild
Fairchild Semiconductor
Description : 8-Line to 3-Line Priority Encoder

General Description
The F148 provides three bits of binary coded output representing the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide Priority encoding over many bits.
   
Features
■ Encodes eight data lines in Priority
■ Provides 3-bit binary Priority code
■ Input enable capability
■ Signals when data is present on any input
■ Cascadable for Priority encoding of n bits
   

Part Name(s) : CD4532BMS
Intersil
Intersil
Description : CMOS 8-Bit Priority Encoder

Description
CD4532BMS consists of combinational logic that encodes the highest Priority input (D7 - D0) to a 3-bit binary code. The eight inputs, D7 through D0, each have an assigned Priority; D7 is the highest Priority and D0 is the lowest. The Priority encoder is inhibited when the chip-enable input E1 is low. When E1 is high, the binary representation of the highestPriority input appears on output lines Q2 - Q0, and the group select line GS is high to indicate that Priority inputs are present. The enable-out (EO) is high when no Priority inputs are present. If any one input is high, EO is low and all cascaded lower-order stages are disabled.

Features
• High Voltage Type (20V Rating)
• Converts From 1 of 8 to Binary
• Provides Cascading Feature to Handle Any Number of Inputs
• Group Select Indicates One or More Priority Inputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
    - 0.5V at VDD = 5V
    - 1.5V at VDD = 10V
    - 1.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications
Priority Encoder
• Binary or BCD Encoder (Keyboard Encoding)
• Floating Point Arithmetic

Description : 2.5V MULTI-Queue FLOW-CONTROL DEVICES (32 QueueS) 18 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits

DESCRIPTION:
The IDT72T51543/72T51553 multi-Queue flow-control devices are single chip within which anywhere between 1 and 32 discrete FIFO Queues can be setup. All Queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective Queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective Queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a Queue maybe selected on the write port and a different Queue on the read port or both ports may select the same Queue simultaneously.

FEATURES:
• Choose from among the following memory density options:
   IDT72T51543  Total Available Memory = 1,179,648 bits
   IDT72T51553  Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
Queues may be configured at master reset from the pool of Total Available Memory in blocks of 512 x 18 or 1,024 x 9
• Independent Read and Write access per Queue
• User programmable via serial port
• User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
• Default multi-Queue device configurations
   – IDT72T51543 : 2,048 x 18 x 32Q
   – IDT72T51553 : 4,096 x 18 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• 200 MHz High speed operation (5ns cycle time)
• 3.6ns access time
• Echo Read Enable & Echo Read Clock Outputs
• Individual, Active Queue flags (OV, FF, PAE, PAF)
• 8 bit parallel flag status on both read and write ports
• Shows PAE and PAF status of 8 Queues
• Direct or polled operation of flag status bus
• Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width)
• User Selectable Bus Matching Options:
   – x18in to x18out
   – x9in to x18out
   – x18in to x9out
   – x9in to x9out
• FWFT mode of operation on read port
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-Queue devices in parallel is available
• Power Down Input provides additional power savings in HSTL and eHSTL modes.
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available

Description : 2.5V MULTI-Queue FLOW-CONTROL DEVICES (32 QueueS) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits

DESCRIPTION:
The IDT72T51546/72T51556 multi-Queue flow-control devices is a single chip within which anywhere between 1 and 32 discrete FIFO Queues can be setup. All Queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective Queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective Queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a Queue maybe selected on the write port and a different Queue on the read port or both ports may select the same Queue simultaneously.

FEATURES:
• Choose from among the following memory density options:
   IDT72T51546  Total Available Memory = 1,179,648 bits
   IDT72T51556  Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36
• Independent Read and Write access per Queue
• User programmable via serial port
• User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
• Default multi-Queue device configurations
   – IDT72T51546 : 1,024 x 36 x 32Q
   – IDT72T51556 : 2,048 x 36 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• 200 MHz High speed operation (5ns cycle time)
• 3.6ns access time
• Echo Read Enable & Echo Read Clock Outputs
• Individual, Active Queue flags (OV, FF, PAE, PAF, PR)
• 8 bit parallel flag status on both read and write ports
• Shows PAE and PAF status of 8 Queues
• Direct or polled operation of flag status bus
• Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width)
• User Selectable Bus Matching Options:
   – x36in to x36out
   – x18in to x36out
   – x9in to x36out
   – x36in to x18out
   – x36in to x9out
• FWFT mode of operation on read port
• Packet mode operation
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-Queue devices in parallel is available
• Power Down Input provides additional power savings in HSTL and eHSTL modes.
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available

Description : 10-Line to 4-Line AND 8-Line to 3-Line Priority Encodeers

The SN74LS147 and the SN74LS148 are Priority Encoders. They provide Priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level.

 

Part Name(s) : HD74HC149
Hitachi
Hitachi -> Renesas Electronics
Description : 8-to-8-line Priority Encoder

Description
The HD74HC149 is Priority encoder which has 8 input lines (0 - 7) and 8 output lies (Y0 - Y7).
It is the logical combination of a HD74HC148 8-3 line Priority encoder driving a HD74HC138 3-8 line decoder.
Only one request output can be low at a time. The output that is low is dependent on the highest Priority request that is low. The order of Priority is 7 highest and 0 lowest.

Features
• High Speed Operation: tpd (0 - 7 to Y) = 16 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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