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ADI
Analog Devices
Description : Low-Power Analog Front End with DSP Microcomputer

GENERAL DESCRIPTION
The AD73411 is a single device incorporating a single analog front end (AFE) and a Microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications.

Part Name(s) : LU850425
Sharp
Sharp Electronics
Description : 8-bit Microcomputer for DSP Camera Systems

DESCRIPTION
The LU850425 is a CMOS 8-bit single-chip Microcomputer for CCD digital camera systems which include a CDS/AGC IC (IR3Y38M), a DSP IC (LR38266), a timing generator IC (LR38578), and this Microcomputer IC.

FEATURES
• Auto exposure control (electronic exposure and mechanical exposure)
• Auto carrier balance tuning
• Auto white balance control
• In combination with an external controller
   (personal computer), functions below can be
   controlled (see "Serial Control Interface" in
   FUNCTIONAL DESCRIPTION)
   ① Switchable :
      AGC/ON/OFF
      Auto white balance/AUTO/PRESET
      Aperture enhancement/ON/OFF
      Back light compensation/ON/OFF
      GAMMA correction/ON/OFF
   ② Electronic shutter speed selection :
      Auto E/E [1/60 (1/50) to 1/70 000 s] or fixed E/E
      [1/60 (1/50), 1/100 (1/60), 1/250, 1/500, 1/1 000,
      1/5 000 and 1/10 000 s]
      ( ) = PAL mode
• Switchable between NTSC and PAL modes
• Single +3.3 V power supply
• Package :
   100-pin LQFP (LQFP100-P-1414) 0.5 mm pin-pitch

Part Name(s) : ADSP-2106X
ADI
Analog Devices
Description : ADSP-2106x SHARC® DSP Microcomputer Family

ADSP-2106x SHARC® DSP Microcomputer Family

GENERAL DESCRIPTION
The ADSP-21061 SHARC—Super Harvard Architecture Computer—is a signal processing Microcomputer that offers new capabilities and levels of performance. The ADSP-21061 SHARC is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dualported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

SUMMARY
    High performance signal processor for communications, graphics, and imaging applications
    Super Harvard Architecture
        Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O
    32-bit IEEE floating-point computation units—multiplier, ALU, and shifter
    Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip
    Integrated multiprocessing features

KEY FEATURES—PROCESSOR CORE
    50 MIPS, 20 ns instruction rate, single-cycle instruction execution
    120 MFLOPS peak, 80 MFLOPS sustained performance
    Dual data address generators with modulo and bit-reverse addressing
    Efficient program sequencing with zero-overhead looping: single-cycle loop setup
    IEEE JTAG Standard 1149.1 test access port and on-chip emulation
    32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format
    240-lead MQFP package, thermally enhanced MQFP, 225-ball plastic ball grid array (PBGA)
    Lead (Pb) free packages. For more information, see Ordering Guide on Page 52.

ADI
Analog Devices
Description : Dual Low Power CMOS Analog Front End with DSP Microcomputer

GENERAL DESCRIPTION
The AD73422 is a single device incorporating a dual analog front end and a Microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

FEATURES
    AFE PERFORMANCE
    Two 16-Bit A/D Converters
    Two 16-Bit D/A Converters
    Programmable Input/Output Sample Rates
    78 dB ADC SNR
    77 dB DAC SNR
    64 kS/s Maximum Sample Rate
    –90 dB Crosstalk
    Low Group Delay (25 s Typ per ADC Channel, 50 s Typ per DAC Channel)
    Programmable Input/Output Gain
    On-Chip Reference

DSP PERFORMANCE
    19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained Performance
    Single-Cycle Instruction Execution
    Single-Cycle Context Switch
    3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
    Multifunction Instructions
    Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 400 Cycle Recovery from Power-Down Condition
    Low Power Dissipation in Idle Mode

ADI
Analog Devices
Description : DSP Microcomputer

GENERAL DESCRIPTION
The ADSP-2192M is a single-chip Microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications, and is ideally suited for PC peripherals.
The ADSP-2192M combines the ADSP-219x family base architecture (three computational units, two data address generators and a program sequencer) into a chip with two core processors (see the Functional Block Diagram on Page 1 and Figure 1).

ADSP-2192M DUAL CORE DSP FEATURES
   320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package
      with PCI, USB, Sub-ISA, and CardBus Interfaces
   3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface
      with Bus Mastering over Four DMA Channels with
      Scatter-Gather Support
   Integrated USB 1.1 Compliant Interface
   Sub-ISA Interface
   AC’97 Revision 2.1 Compliant Interface for External
      Audio, Modem, and Handset Codecs with DMA
      Capability
   Dual ADSP-219x Core Processors (P0 and P1) on Each
      ADSP-2192M DSP Chip
   132K Words of Memory Includes 4K x 16-Bit Shared
      Data Memory
   80K Words of On-Chip RAM on P0, Configured as
      64K Words On-Chip 16-Bit RAM for Data Memory and
      16K Words On-Chip 24-Bit RAM for Program Memory
   48K Words of On-Chip RAM on P1, Configured as
      32K Words On-Chip 16-Bit RAM for Data Memory and
      16K Words On-Chip 24-Bit RAM for Program Memory
   4K Words of Additional On-Chip RAM Shared by Both
      Cores, Configured as 4K Words On-Chip 16-Bit RAM
   Flexible Power Management with Selectable Power Down and Idle Modes
   Programmable PLL Supports Frequency Multiplication,
      Enabling Full Speed Operation from Low Speed
      Input Clocks
   2.5 V Internal Operation Supports 3.3 V/5.0 V
      Compliant I/O

DSP CORE FEATURES
   6.25 ns Instruction Cycle Time (Internal), for up to
      160 MIPS Sustained Performance
   ADSP-218x Family Code Compatible with the Same Easy
      to Use Algebraic Syntax
   Single-Cycle Instruction Execution
   Dual Purpose Program Memory for Both Instruction and
      Data Storage
   Fully Transparent Instruction Cache Allows Dual Operand
      Fetches in Every Instruction Cycle
   Unified Memory Space Permits Flexible Address
      Generation, Using Two Independent DAG Units
   Independent ALU, Multiplier/Accumulator, and Barrel
      Shifter Computational Units with Dual 40-Bit
      Accumulators
   Single-Cycle Context Switch between Two Sets of
      Computational and DAG Registers
   Parallel Execution of Computation and Memory
      Instructions
   Pipelined Architecture Supports Efficient Code Execution
      at Speeds up to 160 MIPS
   Register File Computations with All Nonconditional,
      Nonparallel Computational Instructions
   Powerful Program Sequencer Provides Zero-Overhead
      Looping and Conditional Instruction Execution
   Architectural Enhancements for Compiled C/C++ Code
      Efficiency
   Architecture Enhancements beyond ADSP-218x Family
      are Supported with Instruction Set Extensions for
      Added Registers, Ports, and Peripherals

Description : DSP Microcomputer

GENERAL DESCRIPTION
The ADSP-2195 DSP is a single-chip Microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2195 combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces.

ADI
Analog Devices
Description : DSP Microcomputer

GENERAL DESCRIPTION
The ADSP-21160N SHARC DSP is the second iteration of the ADSP-21160. Built in a 0.18 micron CMOS process, it offers higher performance and lower power consumption than its predecessor, the ADSP-21160M. Easing portability, the ADSP-21160N is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor’s SIMD (Single Instruction, Multiple Data) capability, some code changes are needed. Like other SHARCs, the ADSP-21160N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160N includes an 95 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.

SUMMARY
   High-Performance 32-Bit DSP—Applications in Audio,
      Medical, Military, Graphics, Imaging, and
      Communication
   Super Harvard Architecture—Four Independent Buses
      for Dual Data Fetch, Instruction Fetch, and
      Nonintrusive, Zero-Overhead I/O
   Backwards-Compatible—Assembly Source Level
      Compatible with Code for ADSP-2106x DSPs
   Single-Instruction-Multiple-Data (SIMD) Computational
      Architecture—Two 32-Bit IEEE Floating-Point
      Computation Units, Each with a Multiplier, ALU,
      Shifter, and Register File
   Integrated Peripherals—Integrated I/O Processor,
      4 M Bits On-Chip Dual-Ported SRAM, Glueless
      Multiprocessing Features, and Ports (Serial, Link,
      External Bus, and JTAG)

Description : DSP Microcomputer

GENERAL DESCRIPTION
The ADSP-2196 DSP is a single-chip Microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2196 combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces.

ADSP-219x DSP CORE FEATURES
   6.25 ns Instruction Cycle Time (Internal), for up to
      160 MIPS Sustained Performance
   ADSP-218x Family Code Compatible with the Same
      Easy -to-Use Algebraic Syntax
   Single-Cycle Instruction Execution
   Up to 16M words of Addressable Memory Space with
      24 Bits of Addressing Width
   Dual Purpose Program Memory for Both Instruction and
      Data Storage
   Fully Transparent Instruction Cache Allows Dual
      Operand Fetches in Every Instruction Cycle
   Unified Memory Space Permits Flexible Address
      Generation, Using Two Independent DAG Units
   Independent ALU, Multiplier/Accumulator, and Barrel
      Shifter Computational Units with Dual 40-bit
      Accumulators
   Single-Cycle Context Switch between Two Sets of
      Computational and DAG Registers
   Parallel Execution of Computation and Memory
      Instructions
   Pipelined Architecture Supports Efficient Code
      Execution at Speeds up to 160 MIPS
   Register File Computations with All Nonconditional,
      Nonparallel Computational Instructions
   Powerful Program Sequencer Provides Zero-Overhead
      Looping and Conditional Instruction Execution
   Architectural Enhancements for Compiled C
      Code Efficiency

Description : ADSP-2106x SHARC® DSP Microcomputer Family

GENERAL DESCRIPTION
The ADSP-21062 SHARC—Super Harvard Architecture Computer—is a signal processing Microcomputer that offers new capabilities and levels of performance. The ADSP-21062 SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-21062 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

SUMMARY
    High Performance Signal Processor for Communications, Graphics and Imaging Applications
    Super Harvard Architecture
        Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O
    32-Bit IEEE Floating-Point Computation Units—Multiplier, ALU, and Shifter
    Dual-Ported On-Chip SRAM and Integrated I/O Peripherals—A Complete System-On-A-Chip
    Integrated Multiprocessing Features

Part Name(s) : HD6805S6
Hitachi
Hitachi -> Renesas Electronics
Description : MCU (Microcomputer Unit)

MCU (Microcomputer Unit)

The HD6805S6 is the 8-bit Microcomputer Unit (MCU) which contains a CPU, on-chip clock, ROM, RAM, I/O and timer. It is designed for the user who needs an economical Microcomputer with the proven capabilities of the HD6800-based instruction set.

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