Part Name
Description
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High Bandwidth Potato Chip
High Bandwidth Potato Chip
High Bandwidth Potato Chip
High Bandwidth Potato Chip
High Bandwidth Potato Chip (Rev : 2010 )
High Bandwidth Potato Chip (Rev : 2010 )
High Bandwidth Potato Chip (Rev : 2010 )
High Bandwidth Potato Chip (Rev : 2010 )
1.65v-3.6v, 16-bit Dual Supply Level Shifting Bidirectional Transceiver with 3 state outputs
1.65v-3.6v, 16-bit Dual Supply Level Shifting Bidirectional Transceiver with 3 state outputs
1.65v-3.6v, 16-bit Dual Supply Level Shifting Bidirectional Transceiver with 3 state outputs
1.65v-3.6v, 16-bit Dual Supply Level Shifting Bidirectional Transceiver with 3 state outputs
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET (Rev : 2009 )
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET (Rev : 2009 )
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET (Rev : 2009 )
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET (Rev : 2009 )
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET (Rev : 2009 )
Wide Bandwidth, 8-Channel, 2:1 Mux/DeMux with Single Enable
Wide Bandwidth, 8-Channel, 2:1 Mux/DeMux with Single Enable
Wide Bandwidth, 8-Channel, 2:1 Mux/DeMux with Single Enable
Wide Bandwidth, 8-Channel, 2:1 Mux/DeMux with Single Enable (Rev : 2008 )
Wide Bandwidth, 8-Channel, 2:1 Mux/DeMux with Single Enable (Rev : 2008 )
Wide Bandwidth, 8-Channel, 2:1 Mux/DeMux with Single Enable (Rev : 2008 )
Wide Bandwidth, 4-Channel, 2:1 Mux/DeMux with Single Enable
Wide Bandwidth, 4-Channel, 2:1 Mux/DeMux with Single Enable
Wide Bandwidth, 4-Channel, 2:1 Mux/DeMux with Single Enable
4-Channel, 2:1 Mux/DeMux Switch w/ Single Enable (Rev : 2007 )
4-Channel, 2:1 Mux/DeMux Switch w/ Single Enable (Rev : 2007 )
4-Channel, 2:1 Mux/DeMux Switch w/ Single Enable (Rev : 2007 )
2-Channel, 2:1 Mux/DeMux Switch w/ Single Enable
2-Channel, 2:1 Mux/DeMux Switch w/ Single Enable
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver