25C320X-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'25C320X-I' PDF : 24 Pages View PDF
25AA320/25LC320/25C320
3.7 Data Protection
3.8 Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A WRITE ENABLE instruction must be issued to
set the write enable latch
• After a byte write, page write or Status register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
The 25XX320 powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A low level on CS is required to enter active state
.
TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN
WP
x
x
0
x
1
Low
x
High
WEL
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Writable
Writable
Status Register
Protected
Writable
Protected
Writable
DS21227E-page 12
2004 Microchip Technology Inc.
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