25L1605DM2C View Datasheet(PDF) - Macronix International
Part Name
Description
MFG CO.
25L1605DM2C
Macronix International
'25L1605DM2C' PDF : 56 Pages View PDF
MX25L1605D
MX25L3205D
MX25L6405D
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out
on SO (see Figure. 15)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status
register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress.
When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch.
When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write
status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept
program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL
bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as
defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To
write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed.
Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE)
and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0"
indicates not in CP mode; "1" indicates in CP mode.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/
ACC) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/ACC
pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted
for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only.
Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
SRWD
Continuously
BP3
BP2
BP1
BP0
WEL
(status register program mode
(level of
(level of
(level of
(level of
(write enable
write protect) (CP mode) protected block) protected block) protected block) protected block)
latch)
0 = normal
1= status program mode
register write
1 = CP
disable mode(default 0)
(note1)
(note1)
(note1)
(note1)
1= write enable
0= not write
enable
Non- volatile bit volatile bit Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit volatile bit
note1: see the table "Protected Area Sizes"
bit0
WIP
(write in
progress bit)
1= write
operation
0= not in write
operation
volatile bit
P/N: PM1290
REV. 1.4, OCT. 01, 2008
19
Share Link: 