25L1605DM2C View Datasheet(PDF) - Macronix International
Part Name
Description
MFG CO.
25L1605DM2C
Macronix International
'25L1605DM2C' PDF : 56 Pages View PDF
MX25L1605D
MX25L3205D
MX25L6405D
Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
SCLK
SI
01 6 789
30 31 31 32
47 48 0 1 6 7 8 20 21 22 23 24 0
70
78
Command
AD (hex)
24-bit address
data in
Byte 0, Byte1
Valid
data in
Command (1) Byte n-1, Byte n
04 (hex)
05 (hex)
high impedance
S0
status (2)
Note: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command
(05 hex), RDPR command (A1 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS# goes
high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command
(04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP mode is ended
Figure 22. Sector Erase (SE) Sequence (Command 20)
CS#
SCLK
0123456789
29 30 31
Command
24 Bit Address
SI
Note: SE command is 20(hex).
20
23 22
210
MSB
Figure 23. Block Erase (BE) Sequence (Command D8)
CS#
SCLK
0123456789
29 30 31
Command
24 Bit Address
SI
Note: BE command is D8(hex).
P/N: PM1290
D8
23 22
MSB
210
40
REV. 1.4, OCT. 01, 2008
Share Link: 