Numonyx™ StrataFlash® Wireless Memory (L18)
7.0
AC Characteristics
7.1
AC Test Conditions
Figure 8: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
Note: AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Figure 9: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Notes:
1.
See the following table for component values.
2.
Test configuration component value for worst case speed conditions.
3.
CL includes jig capacitance.
Table 11: Test configuration component value for worst case speed conditions
1.35 V Standard Test
1.7 V Standard Test
Test Configuration
CL (pF)
30
30
Figure 10: Clock Input AC Waveform
VIH
CLK [C]
VIL
R202
R201
R203
Datasheet
26
November 2007
251902-12