A3967
Microstepping Driver with Translator
Pin-out Diagram
Terminal List
REF 1
÷8
RC2 2
PWM
TIMER
24 PFD
23 RC1
SLEEP 3
22 RESET
OUT2B 4
LOAD
SUPPLY2
5 VBB2
GND 6
21 OUT1B
LOAD
VBB1 20 SUPPLY1
19 GND
GND 7
18 GND
SENSE2 8
17 SENSE1
OUT2A 9
16 OUT1A
STEP 10
DIR 11
MS1 12
TRANSLATOR
15 ENABLE
& CONTROL
LOGIC
VCC
14
LOGIC
SUPPLY
13 MS2
Dwg. PP-075-2
Terminal
Name
REF
RC2
SLEEP
OUT2B
LOAD SUPPLY2
GND
SENSE2
OUT2A
STEP
DIR
MS1
MS2
LOGIC SUPPLY
ENABLE
OUT1A
SENSE1
GND
LOAD SUPPLY1
OUT1B
RESET
RC1
PFD
Terminal Description
Gm reference input
Analog input for fixed offtime – bridge 2
Logic input
H bridge 2 output B
VBB2, the load supply for bridge 2
Analog and power ground
Sense resistor for bridge 2
H bridge 2 output A
Logic input
Logic Input
Logic input
Logic input
VCC, the logic supply voltage
Logic input
H bridge 1 output A
Sense resistor for bridge 1
Analog and power ground
VBB1, the load supply for bridge 1
H bridge 1 output B
Logic input
Analog Input for fixed offtime – bridge 1
Mixed decay setting
Terminal
Number
1
2
3
4
5
6, 7
8
9
10
11
12
13
14
15
16
17
18, 19
20
21
22
23
24
Allegro MicroSystems, Inc.
14
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com