3D3215M-5 View Datasheet(PDF) - Data Delay Devices
Part Name
Description
MFG CO.
'3D3215M-5' PDF : 4 Pages View PDF
3D3215
APPLICATION NOTES (CONT’D)
identification, the part number will include a
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D3215 delay line utilizes novel
and innovative compensation circuitry to
minimize the delay variations induced by
fluctuations in power supply and/or temperature.
The thermal coefficient is reduced to 200 PPM/C,
which is equivalent to a variation, over the 0C-
70C operating range, of ±1% or 0.25ns
(whichever is greater) from the 25C delay
settings. The power supply coefficient is reduced,
over the 3.0V-3.6V operating range, to ±1% or
1ns (whichever is greater) of the delay settings at
the nominal 3.3VDC power supply.
The temperature and power supply sensitivities
are based on the measured delay of Tap 5 with
respect to Tap 1. The sensitivity of the Input-to-
Tap 1 delay will be somewhat higher, particularly
with the smaller dash numbers.
It is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
VDD
VIN
IIN
TSTRG
TLEAD
-0.3
7.0
V
-0.3
VDD+0.3
V
-1.0
1.0
mA
25C
-55
150
C
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 3.0V to 3.6V)
PARAMETER
SYMBOL MIN
Static Supply Current*
IDD
High Level Input Voltage
VIH
2.0
Low Level Input Voltage
VIL
High Level Input Current
IIH
-0.1
Low Level Input Current
IIL
-0.1
High Level Output Current
IOH
Low Level Output Current
IOL
6.0
Output Rise & Fall Time
TR & TF
TYP
1.3
0.0
0.0
-8.0
7.5
2
MAX
2.0
0.8
0.1
0.1
-6.0
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
VDD = 3.6V
VIH = VDD
VIL = 0V
VDD = 3.0V
VOH = 2.4V
VDD = 3.0V
VOL = 0.4V
CLD = 5 pf
*IDD(Dynamic) = 5 * CLD * VDD * F
where: CLD = Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
Doc #01014
DATA DELAY DEVICES, INC.
3
12/3/01
3 Mt. Prospect Ave. Clifton, NJ 07013
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