5962H9684503VXC View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
MFG CO.
'5962H9684503VXC' PDF : 21 Pages View PDF
Address
CE
R/ W
Data in
Data out
tWC
tSCE
tAW
tS A
tPWE
tH A
tWHWL
tHZWE
tSD
tHD
DATA VALID
tLZWE
HIGH IMPEDANCE
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/ W LOW. Both signals must be LOW to initialize a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the sig-
nal that terminates the write.
2. R/W must be HIGH during all address transactions.
3. Data I/O pins enter high impedance even if OE is held LOW during
write.
Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)
11
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