74GTL1655A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
74GTL1655A
STMicroelectronics
'74GTL1655A' PDF : 16 Pages View PDF
74GTL1655A
16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS
TRANSCEIVERS WITH LIVE INSERTION
s HIGH SPEED GTL/GTL+ UNIVERSAL
TRANSCEIVER:
tPD = 4.6 ns (MAX.) A to B at VCC = 3V
s COMBINES D-TYPE LATCHES AND D-TYPE
FLIP-FLOPS FOR OPERATION IN
TRANSPARENT, LATCHED, OR CLOCKED
MODE
TSSOP
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 3.0V to 3.6V
s SYMMETRICAL OUTPUT IMPEDANCE:
) |IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT)
t(s s OUTPUT IMPEDANCE:
IOL = 100mA (MIN) at VCC = 3V (B PORT)
c s HIGH-IMPEDANCE STATE DURING POWER
du UP AND POWER DOWN up to
ro VCC=BIASVCC=1.5V PERMITT LIVE
INSERTION
P s B-PORT PRECHARGED BY BIASVCC
te REDUCE NOISE ON THE LINE DURING
le LIVE INSERTION
o s EDGE RATE-CONTROL INPUT
s CONFIGURES THE B-PORT OUTPUT RISE
b AND FALL TIMES
O s BUS HOLD ON DATA INPUTS ELIMINATES
- THE NEED FOR EXTERNAL PULL-UP/
) PULL-DOWN RESISTORS (A PORT)
t(s s DISTRIBUTED VCC AND GND PIN
c CONFIGURATION MINIMIZES HIGH-SPEED
u SWITCHING NOISE IN PARALLEL
d COMUNICATIONS
ro s PIN AND FUNCTION COMPATIBLE WITH
P 74 SERIES 1655
te DESCRIPTION
le The 74GTL1655A devices are 16-bit high-drive
o (100mA), low-output-impedance universal bus
bstransceivers designed for backplane applications.
OThe 74GTL1655A devices provide live-insertion
Table 1: Order Codes
PACKAGE
TSSOP
T&R
74GTL1655ATTR
Figure 1: Pin Connection
capability for backplane applications by tolerating
active signals on the data ports when the devices
are powered off. In addition, a biasing pin
preconditions the GTL/GTL+ port to minimize
disruption to an active backplane.
The edge rate-control (VERC) input is provided so
the rise and fall time of the B outputs can be
configured to optimize for various backplane
loading conditions. Data flow in each direction is
October 2004
Rev. 1
1/16
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