9S12DT128DGV2 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12DT128DGV2' PDF : 142 Pages View PDF
Device User Guide — 9S12DT128DGV2/D V02.16
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
EXTAL
XTAL
CRG
bus clock
oscillator clock
core clock
HCS12 CORE
BDM CPU
MEBI MMC
INT BKP
Flash
RAM
EEPROM
ECT
ATD0, 1
PWM
SCI0, SCI1
SPI0, 1
CAN0, 1, 4
IIC
BDLC
PIM
BF
Figure 3-1 Clock Connections
Freescale Semiconductor
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