9S12HY32 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HY32' PDF : 790 Pages View PDF
Port Integration Module (S12HYPIMV1)
Table 2-2. Block Memory Map (continued)
Port
Offset or
Address
Register
Access Reset Value Section/Page
U 0x0290 PTU—Port U Data Register
R/W
0x0291 PTIU—Port U input Register
R
0x0292 DDRU—Port U Data Direction Register
R/W
0x0293 PIM Reserved
R
0x0294 PERU—Port U Pull Device Enable Register
R/W
0x0295 PPSU—Port U Polarity Select Register
R/W
0x0296 SRRU—Port U Slew Rate Register
R/W
0x0297 PIM Reserved
R
V 0x0298 PTV—Port V Data Register
R/W
0x0299 PTIV—Port V Input Register
R
0x029A DDRV—Port V Data Direction Register
R/W
0x029B PIM Reserved
R
0x029C PERV—Port V Pull Device Enable Register
R/W
0x029D PPSV—Port V Polarity Select Register
R/W
0x029E SRRV—Port V Slew Rate Register
R/W
0x029F PIM Reserved
R
1 Refer to memory map in SoC Guide to determine related module
2 Write access not applicable for one or more register bits. Refer to register description
3 Read always returns logic level on pins.
0x00
3
0x00
0x00
0x00
0x00
0x00
0x00
0x00
3
0x00
0x00
0x00
0x00
0x00
0x00
2.3.73/2-116
2.3.74/2-117
2.3.75/2-117
2.3.76/2-118
2.3.77/2-118
2.3.78/2-119
2.3.79/2-119
2.3.80/2-120
2.3.81/2-121
2.3.82/2-123
2.3.83/2-123
2.3.84/2-125
2.3.85/2-126
2.3.86/2-126
2.3.87/2-127
2.3.88/2-127
Register
Name
Bit 7
6
5
4
0x0000 R
PORTA W
PA7
PA6
PA5
PA4
0x0001 R
PORTB W
PB7
PB6
PB5
PB4
0x0002 R
DDRA W DDRA7
DDRA6
DDRA5
DDRA4
0x0003 R
DDRB W DDRB7
DDRB6
DDRB5
DDRB4
0x0004 R
0
0
0
0
-0x0009 W
Reserved
= Unimplemented or Reserved
3
PA3
PB3
DDRA3
DDRB3
0
2
PA2
PB2
DDRA2
DDRB2
0
1
PA1
PB1
DDRA1
DDRB1
0
Bit 0
PA0
PB0
DDRA0
DDRB0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
Freescale Semiconductor
63
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