9S12HY32 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HY32' PDF : 790 Pages View PDF
Port Integration Module (S12HYPIMV1)
1 Read: Anytime.
Write: Anytime.
Table 2-29. DDRP Register Field Descriptions
Field
7
DDRP
Description
Port P data direction—
This register controls the data direction of pin 7.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this
pin is forced to be an input. In these cases the data direction bit will not change.
6-0
DDRP
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P data direction—
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel.
In this case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
2.3.34 Port P Reduced Drive Register (RDRP)
Address 0x025B
R
W
Reset
7
RDRP7
0
1 Read: Anytime.
Write: Anytime.
6
RDRP6
5
RDRP5
4
RDRP4
3
RDRP3
2
RDRP2
0
0
0
0
0
Figure 2-32. Port P Reduced Drive Register (RDRP)
Access: User read/write1
1
0
RDRP1
RDRP0
0
0
Table 2-30. RDRP Register Field Descriptions
Field
7-0
RDRP
Description
Port P reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
Freescale Semiconductor
93
Share Link: 
