9S12HY48 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HY48' PDF : 790 Pages View PDF
Port Integration Module (S12HYPIMV1)
2.3.51 Port AD Data Direction Register (DDR1AD)
Address 0x0273
7
R
DDR1AD7
W
Reset
0
1 Read: Anytime
Write: Anytime
6
5
4
3
2
DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2
0
0
0
0
0
Figure 2-49. Port AD Data Direction Register (DDR1AD)
Access: User read/write1
1
0
DDR1AD1 DDR1AD0
0
0
Table 2-44. DDR1AD Register Field Descriptions
Field
Description
7-0 Port AD data direction—
DDR1AD This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT1AD registers, when changing the
DDR1AD register.
2.3.52 PIM Reserved Register
Address 0x0274
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 Read: Always reads 0x00
Write: Unimplemented
Figure 2-50. PIM Reserved Register
Access: User read1
1
0
0
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
104
Freescale Semiconductor
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