9S12XB128 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

9S12XB128

S12XD & S12XB & S12XA Families

Freescale Semiconductor 

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Chapter 1 Device Overview MC9S12XD-Family

1.2.2 Signal Properties Summary

Table 1-7 summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts

of the S12XD, S12XB and S12XA family please refer to Appendix E Derivative Differences.

Table 1-7. Signal Properties Summary (Sheet 1 of 4)

Pin

Name

Function 1

Pin

Name

Function 2

Pin

Name

Function 3

Pin

Name

Function 4

Pin

Name

Function 5

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

Description

EXTAL

—

—

—

—

VDDPLL

NA

NA Oscillator pins

XTAL

—

—

—

—

VDDPLL

NA

NA

RESET

—

—

—

—

VDDR

PULLUP

External reset

TEST

—

—

—

—

N.A. RESET pin DOWN Test input

VREGEN

—

—

—

—

VDDX

PUCR

Up Voltage regulator enable

Input

XFC

—

—

—

—

VDDPLL

NA

NA PLL loop filter

BKGD

MODC

—

—

—

VDDX Always on

Up Background debug

PAD[23:08] AN[23:8]

—

—

—

VDDA

PER0/ Disabled Port AD I/O, Port AD inputs

PER1

of ATD1 and

analog inputs of ATD1

PAD[07:00] AN[7:0]

—

—

—

VDDA

PER1 Disabled Port AD I/O, Port AD inputs

of ATD0 and

analog inputs of ATD0

PA[7:0]

—

—

—

PB[7:0]

—

—

—

PA[7:0] ADDR[15:8] IVD[15:8]

—

—

VDDR

PUCR Disabled Port A I/O

—

VDDR

PUCR Disabled Port BI/O

—

VDDR

PUCR Disabled Port A I/O, address bus,

internal visibility data

PB[7:1] ADDR[7:1] IVD[7:0]

—

—

VDDR

PUCR Disabled Port B I/O, address bus,

internal visibility data

PB0

ADDR0

UDS

VDDR

PUCR

Disabled Port B I/O, address bus,

upper data strobe

PC[7:0] DATA[15:8]

—

—

PD[7:0] DATA[7:0]

—

—

PE7

ECLKX2 XCLKS

—

—

VDDR

PUCR Disabled Port C I/O, data bus

—

VDDR

PUCR Disabled Port D I/O, data bus

—

VDDR

PUCR

Up Port E I/O, system clock

output, clock select

PE6

TAGHI

MODB

—

—

VDDR

While RESET

Port E I/O, tag high, mode

pin is low: down input

PE5

RE

MODA TAGLO

—

VDDR

While RESET

Port E I/O, read enable,

pin is low: down mode input, tag low input

PE4

ECLK

—

—

—

VDDR

PUCR

PE3

LSTRB

LDS EROMCTL

—

VDDR

PUCR

Up Port E I/O, bus clock output

Up Port E I/O, low byte data

strobe, EROMON control

PE2

R/W

WE

—

PE1

IRQ

—

—

—

VDDR

PUCR

—

VDDR

PUCR

Up Port E I/O, read/write

Up Port E Input, maskable

interrupt

MC9S12XDP512 Data Sheet, Rev. 2.21

52

Freescale Semiconductor

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