9S12XDG128 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12XDG128' PDF : 1348 Pages View PDF
Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.1 Module Memory Map
Table 2-1 gives an overview on all CRG registers.
Table 2-1. CRG Memory Map
Address
Offset
Use
0x_00
CRG Synthesizer Register (SYNR)
0x_01
0x_02
CRG Reference Divider Register (REFDV)
CRG Test Flags Register (CTFLG)1
0x_03
CRG Flags Register (CRGFLG)
0x_04
CRG Interrupt Enable Register (CRGINT)
0x_05
CRG Clock Select Register (CLKSEL)
0x_06
CRG PLL Control Register (PLLCTL)
0x_07
CRG RTI Control Register (RTICTL)
0x_08
0x_09
0x_0A
CRG COP Control Register (COPCTL)
CRG Force and Bypass Test Register (FORBYP)2
CRG Test Control Register (CTCTL)3
0x_0B
CRG COP Arm/Timer Reset (ARMCOP)
1 CTFLG is intended for factory test purposes only.
2 FORBYP is intended for factory test purposes only.
3 CTCTL is intended for factory test purposes only.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
83
Share Link: 
