A2550KLPTR View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A2550KLPTR' PDF : 15 Pages View PDF
A2550
Relay Driver with 5 V Regulator
for Automotive Applications
Applications Information
NPOR is pulsed for a watchdog fault. For the remaining
faults, NPOR is held low for the duration of the fault. After
the fault condition is removed, NPOR remains low during
the tPOR period. The latter is set by the value of the external
capacitor fed by a current source at the CPOR pin, according
to the following formula:
tPOR
=
⎛⎝200
ms
µF
⎞
⎠
CPOR
(2)
The scaling factor is simply derived from the specifications
using the typical value of IPOR:
t POR
CPOR
=
VREF
− VTRIP(L)
I POR
(3)
Watchdog
The watchdog monitors the microcontroller to detect if
it locks up. To do so, the watchdog checks for pulses on
the Watchdog Input pin (WDI), and if they are absent for
longer than the timeout period, tWD , the watchdog activates
NPOR, which pulses periodically. tWD is proportional to
the external capacitor fed by a current source at the CWD
pin. The voltage change is 1 V, so using the typical value of
ICWD(charging) we have:
tWD =
⎛200
⎝
ms
µF
⎞
⎠
CWD
(4)
The pulse width for NPOR active, tWDR, also scales propor-
tionally to the value of the external capacitor at the CWD
pin. Using the typical value of ICWD(discharging) we have:
tWDR =
⎛14
⎝
ms
µF
⎞
⎠
CWD
(5)
See the specification tables for tolerances.
When not used, disable watchdog by tying WDI to NPOR
and tying CWD low. Table 2 shows watchdog timing for the
nominal capacitances listed.
Table 2. Timing Set by Capacitors
C
(μF)
tPOR
(ms)
tWD
(ms)
tWDR
(ms)
0.1
20
20
1
0.22
44
44
3
0.47
94
94
7
1
200
200
14
Output Overcurrent
When the OC (overcurrent) protection is triggered in a
driver, that driver is disabled for self-protection. No other
functions are affected; NPOR and VREG5 operate nor-
mally. A disabled output driver remains shut down until the
respective INx is brought low, then high again; at which time
OUTx turns on. OUTx will switch on again the next time
INx is applied. If a short-to-battery still exists, the overcur-
rent will trip each time INx is reapplied.
Sleep
The A2550 is put to sleep by holding both EN and ENBAT
low. In sleep mode all functions are shut down, including
VREG5. If the VREG5 regulator is required at all times, dis-
able sleep mode by tying ENBAT to VBB.
Power Limits
Power dissipation, PD , is limited by thermal constraints. The
maximum allowed power dissipation, PD(max) , is found from
the formula:
TJ = (PD(max) RθJA+ TA) ≤ TJ(max)
(6)
The maximum junction temperature, TJ(max) , and the thermal
resistance, RθJA , are given in the specification tables.
The three main contributors to power dissipation are:
• PBIAS from the supply bias current
• PREG from the linear regulator voltage drop
• PLS from low-side driver conduction
For example, to determine if TJ is in an acceptable range,
given:
RθJA = 55°C/W , and
TA = 125°C ; and
PBIAS = VBB × IBBQ
(7)
= 14 V × 3 mA = 42 mW , and
PREG = (VBB – VREG5(min)) × IREG5
(8)
= (14 V – 4.9 V) × 20 mA= 182 mW , and
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Share Link: 
