A29DL32x Series
AC CHARACTERISTICS
Read Only Operations
Parameter
Description
Test Setup
Speed
Unit
JEDEC Std
tAVAV tRC Read Cycle Time (Note 1)
-70
-80
-90 -120
Min. 70
80
90
120
ns
tAVQV tACC Address to Output Delay
CE = VIL
OE = VIL Max.
70
80
90
120
ns
tELQV tCE Chip Enable to Output Delay
OE = VIL Max. 70
80
90
120
ns
tGLQV tOE Output Enable to Output Delay
Max. 30
30
40
50
ns
tEHQZ
tGHQZ
tAXQX
tDF Chip Enable to Output High Z
(Notes 1,3)
tDF Output Enable to Output High Z
(Notes 1,3)
Output Hold Time from Addresses,
tOH CE or OE , Whichever Occurs First
Max. 16
16
16
16
ns
Max. 16
16
16
16
ns
Min.
0
ns
Read
tOEH Output Enable Hold
Min.
0
ns
Time (Note 1)
Toggle and
Min.
10
ns
Data Polling
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 14 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from OE high to
the data bus driven to VCC/2 is taken as tDF.
Figure 11. Read Operation Timings
Addresses
CE
OE
WE
Output
tRH
tRH
tOEH
High-Z
tRC
Addresses Stable
tACC
tOE
tCE
tDF
tOH
Output Valid
High-Z
RESET
RY/BY 0V
PRELIMINARY (May, 2005, Version 0.0)
33
AMIC Technology, Corp.