A3949SLB View Datasheet(PDF) - Allegro MicroSystems

Part Name

Description

MFG CO.

A3949SLB

DMOS Full-Bridge Motor Driver

Allegro MicroSystems 

1 2 3 4 5 6 7 8

MODE

PHASE

ENABLE

SLEEP

A3949

DMOS Full-Bridge Motor Driver

Functional Block Diagram

.22 μF

25 V

VREG

0.1 μF

CP1

CP2

Low Side

Gate Supply

OSC

Charge

Pump

VCP

VBB

0.1 μF

Load

Supply

0.1 μF

100 μF

Control

Logic

DMOS Full Bridge

OUTA

OUTB

SENSE

GND

GND

Control Logic Table

PHASE ENABLE MODE SLEEP OUTA OUTB

Function

1

1

X

1

H

L

Forward

0

1

X

1

L

H

Reverse

X

0

1

1

L

L

Brake (slow decay)

1

0

0

1

L

H

Fast decay SR*

0

0

0

1

H

L

Fast decay SR*

X

X

X

0

Hi-Z

Hi-Z

Sleep mode

* To prevent reversal of current during fast decay SR (synchronous rectification), the outputs

go to the high impedance state as the current approaches zero.

2

www.allegromicro.com

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

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