A3985SLDTR-T View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A3985SLDTR-T' PDF : 15 Pages View PDF
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
to 0 disables Bridge 1, with all drivers off (see Internal PWM
Current Control, in the Functional Description section).
D7 – Bridge 1 Phase Controls the direction of output cur-
rent for Bridge (load) 1.
D7 S1A S1B
0
L
H
1
H
L
D8 – Bridge 1 Mode Determines whether slow decay is
forced or mixed decay, according to Word 1 Bits D3 to D11,
is allowed.
D8
Mode
0 Mixed-decay
1 Slow-decay
D9 – D14 Bridge 2 Linear DAC These six bits set the
desired current level for Bridge 2. Setting all six bits to 0
disables Bridge 2, with all drivers off (see Internal PWM
Current Control, in the Functional Description section).
D15 – Bridge 2 Phase Controls the direction of output
current for Bridge (load) 2.
D15 S2A S2B
0
L
H
1
H
L
D16 – Bridge 2 Mode Determines whether slow decay is
forced or mixed decay, according to Word 1 Bits D3 to D11,
is allowed.
D16
Mode
0 Mixed-decay
1 Slow-decay
D17 and D18 – Gm Range Select These bits determine
the range scaling factor, Gm , used in PWM current control,
according to the following formula:
ITripDAC = VDAC / (Gm × RSENSEx)
D18 D17
Gm
0
0
8
0
1
12
1
0
16
1
1
20
Control Register (Word 1) Bit Assignments
This section describes the function of the individual bit val-
ues in the Control register, one of the two registers accessed
through the serial port. The assignments are summarized in
the Bit Assignments table.
Note that the Control register can only be updated when the
WC pin is logic low.
D0 – Register Select Indicates which register should
receive the data. For the Control register, this is set to 1.
D1 and D2 – Blank Time These two bits set the value of
the scaling factor, α / fMCK, used for determining tBLANK for
the current-sense comparator. The factor for tDEAD also is set,
because tDEAD = tBLANK / 2 .
D2
D1
tBLANK
tDEAD
(tBLANK/ 2)
0
0
4 / fMCK
2 / fMCK
0
1
6 / fMCK
3 / fMCK
1
0
8 / fMCK
4 / fMCK
1
1
12 / fMCK
6 / fMCK
D3 through D7 – Fixed Off Time These five bits set the
fixed off-time for the internal PWM control circuitry. Fixed
off-time is defined by:
tOFF = [(1 + n) × (8 / fMCK)] – 1 / fMCK ,
where n = 0 to 31.
For example, with a master clock frequency of 4 MHz, the
fast-decay time would be adjustable within the range
1.75 to 63.75 μs, in increments of 2 μs.
D8 through D11 – Fast Decay Time These four bits set
the fast decay portion of fixed off-time for the internal PWM
control circuitry. The fast-decay portion is defined by:
tFD = [(1 + n) × 8 / fMCK)] – 1 / fMCK ,
where n = 0 to 15.
For example, with a master clock frequency of 4 MHz, the
fast decay time would be adjustable within the range
1.75 to 32.75 μs, in increments of 2 μs.
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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