A3986SLDTR View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A3986SLDTR' PDF : 16 Pages View PDF
A3986
Dual Full-Bridge MOSFET Driver
with Microstepping Translator
C1A, C1B, C2A, and C2B High-side connections for the
bootstrap capacitors, CBOOTx, and positive supply for high-
side gate drivers. The bootstrap capacitors are charged to
approximately VREG when the associated output Sxx terminal
is low. When the output swings high, the voltage on this ter-
minal rises with the output to provide the boosted gate volt-
age needed for the high-side N-channel power MOSFETs.
The bootstrap capacitor should be ceramic and have a value
of 10 to 20 times the total MOSFET gate capacitance.
GH1A, GH1B, GH2A, and GH2B High-side gate drive
outputs for external N-channel MOSFETs. External series
gate resistors can be used to control the slew rate seen at
the gate, thereby controlling the di/dt and dv/dt at the motor
terminals. GHxx = 1 (high) means that the upper half of the
driver is turned on and will source current to the gate of the
high-side MOSFET in the external motor-driving bridge.
GHxx = 0 (low) means that the lower half of the driver is
turned on and will sink current from the external MOSFET’s
gate circuit to the respective Sxx pin.
S1A, S1B, S2A, and S2B Directly connected to the
motor, these terminals sense the voltages switched across the
load and define the negative supply for the floating high-side
drivers. The discharge current from the high-side MOSFET
gate capacitance flows through these connections which
should have low impedance traces to the MOSFET bridge.
GL1A, GL1B, GL2A, and GL2B Low-side gate drive
outputs for external N-channel MOSFETs. External series
gate resistors (as close as possible to the MOSFET gate)
can be used to reduce the slew rate seen at the gate, thereby
controlling the di/dt and dv/dt at the motor terminals.
GLxx = 1 (high) means that the upper half of the driver is
turned on and will source current to the gate of the low-side
MOSFET in the external motor-driving bridge. GLxx = 0
(low) means that the lower half of the driver is turned on and
will sink current from the gate of the external MOSFET to
the LSSx pin.
LSS1 and LSS2 Low-side return path for discharge of the
gate capacitors, connected to the common sources of the
low-side external FETs through low-impedance traces.
Motor Control
Motor speed and direction is controlled simply by two logic
inputs, and the microstep level is controlled by a further two
logic inputs. At power-up or reset, the translator sets the
DACs and phase current polarity to the initial Home state
(see figures 2 through 5 for home-state conditions), and sets
the current regulator for both phases to mixed-decay mode.
When a step command signal occurs on the STEP input, the
translator automatically sequences the DACs to the next
level (see table 3 for the current level sequence and current
polarity).
The microstep resolution is set by inputs MS1 and MS2 as
shown in table 1. If the new DAC level is higher or equal to
the previous level, then the decay mode for that full-bridge
will be slow decay. If the new DAC output level is lower
than the previous level, the decay mode for that full-bridge
will be set by the PFD1 and PFD2 inputs. This automatic
current-decay selection improves microstepping performance
by reducing the distortion of the current waveform due to the
motor BEMF.
STEP A low-to-high transition on the STEP input sequences
the translator and advances the motor one increment. The
translator controls the input to the DACs as well as the direc-
tion of current flow in each winding. The size of the incre-
ment is determined by the state of the MSx inputs.
MS1 and MS2 These Microstep Select inputs are used
to select the microstepping format, per table 1. Changes to
these inputs do not take effect until the next STEP input ris-
ing edge.
DIR This Direction input determines the direction of rotation
of the motor. When low, the direction is “clockwise” and
“counterclockwise” when high. A change on this input does
not take effect until the next STEP rising edge.
Internal PWM Current Control
Each full-bridge is independently controlled by a fixed off-
time PWM current control circuit that limits the load current
in the phase to a desired value, ITRIP. Initially, a diagonal pair
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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