A3986SLDTR-T View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A3986SLDTR-T' PDF : 16 Pages View PDF
A3986
Dual Full-Bridge MOSFET Driver
with Microstepping Translator
PFD1 and PFD2 The Percent Fast Decay pins are used
to select the portion of fast decay, according to table 2, to be
used when mixed decay is enabled. Mixed decay is enabled
when a STEP input signal commands an output current that
is lower than for the previous step. In mixed decay mode,
as the trip point is reached, the A3986 goes into fast decay
mode until the specified number of master oscillator cycles
has completed. After this fast decay portion, the A3986
switches to slow decay mode for the remainder of the fixed
off-time, tOFF.
Using PFD1 and PFD 2 to select 0% fast decay will effec-
tively maintain the full-bridge in slow decay at all times.
This option can be used to keep the phase current ripple to
a minimum when the motor is stationary or stepping at very
low rates.
Selecting 100% fast decay will provide the fastest current
control when the current is falling and can help when the
motor is being driven at very high step rates.
SR Input used to set synchronous rectification mode. When
a PWM off-cycle is triggered, load current recirculates
according to the decay mode selected by the control logic.
The synchronous rectification feature turns on the appropri-
ate MOSFETs during the current decay and effectively shorts
out the body diodes with the low RDS(ON) of the MOSFET.
This lowers power dissipation significantly and eliminates
the need for additional Schottky diodes. Synchronous
rectification can be set to either active mode or disabled
mode.
• Active Mode When the SR pin input is logic low, active
mode is enabled and synchronous rectification will occur.
This mode prevents reversal of the load current by turning
off synchronous rectification when a zero current level is
detected. This prevents the motor winding from conduct-
ing in the reverse direction.
• Disabled Mode When the SR pin input is logic high, syn-
chronous rectification is disabled. This mode is typically
used when external diodes are required to transfer power
dissipation from the power MOSFETs to external, usually
Schottky, diodes.
Shutdown Operation In the event of an overtempera-
ture fault, or an undervoltage fault on VREG, the MOS-
FETs are disabled until the fault condition is removed. At
power-up, and in the event of low voltage at VDD, the under
voltage lockout (UVLO) circuit disables the MOSFETs until
the voltage at VDD reaches the minimum level. Once VDD is
above the minimum level, the translator is reset to the home
state, and the MOSFETs are reenabled.
Allegro MicroSystems, Inc.
13
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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