A4401L View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A4401L' PDF : 17 Pages View PDF
A4401
Automotive Quasi-Resonant Flyback Control IC
where IOUT is the maximum load current, and D'(max)
is the duty cycle, limited to 0.3.
Then the rms current in the winding is:
IRMS
=
IPK ×
⎛
⎜⎜
⎝
D'
3
⎞½
⎟⎟
⎠
,
(32)
Because the number of turns has already been worked
out, the ampere-turns factor can now be determined.
After all of the ampere-turns are known for each wind-
ing, the bobbin window can be apportioned to each
winding. It is recommended that the current density in
each winding should be kept below 5 A per mm2.
Another consideration when selecting the wire gauge
is the skin depth (depth within which the current
flows), especially at higher frequencies. Skin depth
can be calculated as:
δ = 75 ,
f½
(33)
SW
For example, if 45 kHz were the minimum frequency
at minimum input voltage and maximum load, then
to ensure maximum wire utilization for the first four
switching harmonics, the switching frequency would
be 180 kHz. The conduction depth at 180 kHz would
equal 0.18 mm, therefore, the wire diameter should
not exceed 0.36 mm. For any particular winding, if the
current rating of the wire is insufficient even though
the wire meets the skin depth criteria, multiple wires
wound in parallel will be necessary.
It is recommended to locate the start and finish of
each winding as close as possible on the bobbin. This
minimizes the “loop area” and reduces the effects of
noise pick-up.
C11 Resonant Capacitor Selection
The resonance that occurs when the MOSFET, Q1,
turns off is formed by the interaction of the primary
magnetizing inductance and the capacitance between
the LX node (the drain terminal of the MOSFET) and
ground. The design is optimized for a half resonant
period of 1 μs. This means the resonant capacitor
value can be found from the following formula:
CRES = ⎜⎜⎛TR
⎝
⎞²
⎟⎟ ×
⎠
1
LPRI
,
(34)
where TR is a half resonant period of 1 μs.
It is advisable to measure the half resonant period in
the application, as the parasitic capacitance between
the LX node and ground can be substantial and may
even be sufficient to meet the requirements with very
little additional capacitance.
PCB Layout Guidelines
The layout can be considered as two blocks: primary
and secondary:
Primary Block To minimize parasitic noise appearing
on the ground return, and at the LX and ISS nodes,
as well as to maximize the effectiveness of the EMI
VBAT
CIN
LPRI
A4401
LX node
MOSFET
Q1
ISS node
RSENSE
When winding the high voltage windings, such as for
the anode or grid, it is advisable to insert a layer of
polyester insulating tape between each layer as well as
between adjacent windings.
Figure 3. Main power loop
Minimize this loop area
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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