A4980KLP-T View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A4980KLP-T' PDF : 44 Pages View PDF
A4980
Automotive, Programmable Stepper Driver
the internal control circuits act on the new configuration and
control data, and the diagnostic registers are reset.
If there are more than 16 rising edges on SCK, or if STRn goes
high and there are fewer than 16 rising edges on SCK, the write
will be cancelled without writing data to the configuration and
control registers. In addition the diagnostic registers will not be
reset. Instead the FF bit will be set to 1 in the diagnostic registers,
to indicate a data transfer error.
SCK remains high while STRn is low. When STRn goes high the
transfer will be terminated and SDO will go into its high imped-
ance state.
Configuration and Run Registers
These registers are used for system configuration and motor con-
trol. Access is described in the section Writing to Configuration
and Control Registers, above.
The first two bits of the serial word are used to select the register
to be written. This provides access to four writable registers:
• The Configuration registers are used for system configuration:
CONFIG0 for system parameters, and CONFIG1 for system
and diagnostic parameters.
• The RUN register contains motor drive settings used to control
the motor movement and phase current.
• The fourth writable register, TBLLD, is a port that allows se-
quential loading of the 16 distinct phase current table settings.
Reading from Diagnostic Registers
In addition to the writable registers there are two diagnostic
registers. The first eight (most significant) bits of both diagnostic
registers contain the same flags, only the last eight (least signifi-
cant) bits differ, as follows:
• FAULT0 contains the short-circuit fault flags
• FAULT1 contains the present Step Angle Number
Each time a configuration and control register is written, one
of the diagnostic registers can be read, MSB first, on the serial
output pin, SDO (see timing in figure 1). FAULT1 is made the
active register for serial transfer and output on SDO only while
CONFIG1 is being written, that is, only when the first bit of the
input word is 0 and the second bit is 1. FAULT0 is the active
register for serial transfer and output on SDO during writes to any
other configuration or control register.
When STRn goes low to start a serial write, SDO comes out of its
high impedance state and outputs the serial register Fault Register
flag. This allows the main controller to poll the A4980 through
the serial interface to determine if a fault has been detected.
If no faults have been detected then the serial transfer may be
terminated without generating a serial read fault by ensuring that
CONFIG0 sets certain system parameters, and CONFIG1 sets
system and diagnostic output selection parameters. The RUN
register contains motor drive settings used to control the motor
movement and phase current.
Phase Table Load Register
This is one of the configuration and control registers, accessed
when both address bits are 1. It can be used to write a sequence
of values to the phase current table in the A4980. This allows
the current at each Step Angle Number to be tailored to suit
the microstep current profile requirements of a specific motor.
In most cases this feature will not be required and the default
sinusoidal profile will suffice. However for some motor / load
combinations, altering the current profile can improve torque
ripple, resulting in lower mechanical vibration and noise.
Although the phase current table contains 64 entries for each of
two phases, only 16 distinct values are required. These 16 values
correspond to one quadrant of the table for a single phase, and
they are repeated for the other three quadrants and again for the
four quadrants of the other phase. So each of the 16 values writ-
ten to the Phase Table Load register are written to 8 locations in
the phase current table.
The 16 values must be entered by sequential writes to the Phase
Table Load register. The first write to the register after writing to
any other register, or after a reset (RESETn pulse low or power-
on), puts that value, PT[5..0], into the first phase table address,
a 6-bit field defined as PT(0). Subsequent writes put values into
successive addresses: PT(1), PT(2), and so forth up to PT(15).
After the sixteenth value has been written, no more values are
accepted and any writes to the Phase Table Load register are
ignored. As each value is received, it is effectively distributed to
all eight required locations in the phase current table.
Allegro MicroSystems, Inc.
17
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Share Link: 
